A 0.357 ps Resolution, 2.4 GHz Time-to-Digital Converter with Phase-Interpolator and Time Amplifier

YoungHwa KIM; AnSoo PARK; Joon-Sung PARK; YoungGun PU; Hyung-Gu PARK; HongJin KIM; Kang-Yoon LEE

doi:10.1587/transele.E94.C.1896

A 0.357 ps Resolution, 2.4 GHz Time-to-Digital Converter with Phase-Interpolator and Time Amplifier

YoungHwa KIM, AnSoo PARK, Joon-Sung PARK, YoungGun PU, Hyung-Gu PARK, HongJin KIM, Kang-Yoon LEE

Full Text Views

0

Share
Cite this

Summary :

In this paper, we propose a two-step TDC with phase-interpolator and time amplifier to satisfy high resolution at 2.4 GHz input frequency by implementing delay time less than that of an inverter delay. The accuracy of phase-interpolator is improved for process variation using the resistor automatic-tuning circuit. The gain of time amplifier is improved using the delay time difference between two delay cells. It is implemented in a 0.13 µm CMOS process with a die area of 0.68 mm². And the power consumption is 14.4 mW at a 1.2 V supply voltage. The resolution and input frequency of the TDC are 0.357 ps and 2.4 GHz, respectively.

Publication: IEICE TRANSACTIONS on Electronics Vol.E94-C No.12 pp.1896-1901

Publication Date: 2011/12/01

Publicized

Online ISSN: 1745-1353

DOI: 10.1587/transele.E94.C.1896

Type of Manuscript: PAPER

Category: Integrated Electronics

Cite this

Copy

YoungHwa KIM, AnSoo PARK, Joon-Sung PARK, YoungGun PU, Hyung-Gu PARK, HongJin KIM, Kang-Yoon LEE, "A 0.357 ps Resolution, 2.4 GHz Time-to-Digital Converter with Phase-Interpolator and Time Amplifier" in IEICE TRANSACTIONS on Electronics, vol. E94-C, no. 12, pp. 1896-1901, December 2011, doi: 10.1587/transele.E94.C.1896.
Abstract: In this paper, we propose a two-step TDC with phase-interpolator and time amplifier to satisfy high resolution at 2.4 GHz input frequency by implementing delay time less than that of an inverter delay. The accuracy of phase-interpolator is improved for process variation using the resistor automatic-tuning circuit. The gain of time amplifier is improved using the delay time difference between two delay cells. It is implemented in a 0.13 µm CMOS process with a die area of 0.68 mm². And the power consumption is 14.4 mW at a 1.2 V supply voltage. The resolution and input frequency of the TDC are 0.357 ps and 2.4 GHz, respectively.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/transele.E94.C.1896/_p

Copy

@ARTICLE{e94-c_12_1896,
author={YoungHwa KIM, AnSoo PARK, Joon-Sung PARK, YoungGun PU, Hyung-Gu PARK, HongJin KIM, Kang-Yoon LEE, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 0.357 ps Resolution, 2.4 GHz Time-to-Digital Converter with Phase-Interpolator and Time Amplifier},
year={2011},
volume={E94-C},
number={12},
pages={1896-1901},
abstract={In this paper, we propose a two-step TDC with phase-interpolator and time amplifier to satisfy high resolution at 2.4 GHz input frequency by implementing delay time less than that of an inverter delay. The accuracy of phase-interpolator is improved for process variation using the resistor automatic-tuning circuit. The gain of time amplifier is improved using the delay time difference between two delay cells. It is implemented in a 0.13 µm CMOS process with a die area of 0.68 mm². And the power consumption is 14.4 mW at a 1.2 V supply voltage. The resolution and input frequency of the TDC are 0.357 ps and 2.4 GHz, respectively.},
keywords={},
doi={10.1587/transele.E94.C.1896},
ISSN={1745-1353},
month={December},}

Copy

TY - JOUR
TI - A 0.357 ps Resolution, 2.4 GHz Time-to-Digital Converter with Phase-Interpolator and Time Amplifier
T2 - IEICE TRANSACTIONS on Electronics
SP - 1896
EP - 1901
AU - YoungHwa KIM
AU - AnSoo PARK
AU - Joon-Sung PARK
AU - YoungGun PU
AU - Hyung-Gu PARK
AU - HongJin KIM
AU - Kang-Yoon LEE
PY - 2011
DO - 10.1587/transele.E94.C.1896
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E94-C
IS - 12
JA - IEICE TRANSACTIONS on Electronics
Y1 - December 2011
AB - In this paper, we propose a two-step TDC with phase-interpolator and time amplifier to satisfy high resolution at 2.4 GHz input frequency by implementing delay time less than that of an inverter delay. The accuracy of phase-interpolator is improved for process variation using the resistor automatic-tuning circuit. The gain of time amplifier is improved using the delay time difference between two delay cells. It is implemented in a 0.13 µm CMOS process with a die area of 0.68 mm². And the power consumption is 14.4 mW at a 1.2 V supply voltage. The resolution and input frequency of the TDC are 0.357 ps and 2.4 GHz, respectively.
ER -