Design Approach and Implementation of Application Specific Instruction Set Processor for SHA-3 BLAKE Algorithm

Yuli ZHANG; Jun HAN; Xinqian WENG; Zhongzhu HE; Xiaoyang ZENG

doi:10.1587/transele.E95.C.1415

Design Approach and Implementation of Application Specific Instruction Set Processor for SHA-3 BLAKE Algorithm

Yuli ZHANG, Jun HAN, Xinqian WENG, Zhongzhu HE, Xiaoyang ZENG

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This paper presents an Application Specific Instruction-set Processor (ASIP) for the SHA-3 BLAKE algorithm family by instruction set extensions (ISE) from an RISC (reduced instruction set computer) processor. With a design space exploration for this ASIP to increase the performance and reduce the area cost, we accomplish an efficient hardware and software implementation of BLAKE algorithm. The special instructions and their well-matched hardware function unit improve the calculation of the key section of the algorithm, namely G-functions. Also, relaxing the time constraint of the special function unit can decrease its hardware cost, while keeping the high data throughput of the processor. Evaluation results reveal the ASIP achieves 335 Mbps and 176 Mbps for BLAKE-256 and BLAKE-512. The extra area cost is only 8.06k equivalent gates. The proposed ASIP outperforms several software approaches on various platforms in cycle per byte. In fact, both high throughput and low hardware cost achieved by this programmable processor are comparable to that of ASIC implementations.

Publication: IEICE TRANSACTIONS on Electronics Vol.E95-C No.8 pp.1415-1426

Publication Date: 2012/08/01

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Online ISSN: 1745-1353

DOI: 10.1587/transele.E95.C.1415

Type of Manuscript: PAPER

Category: Electronic Circuits

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Yuli ZHANG, Jun HAN, Xinqian WENG, Zhongzhu HE, Xiaoyang ZENG, "Design Approach and Implementation of Application Specific Instruction Set Processor for SHA-3 BLAKE Algorithm" in IEICE TRANSACTIONS on Electronics, vol. E95-C, no. 8, pp. 1415-1426, August 2012, doi: 10.1587/transele.E95.C.1415.
Abstract: This paper presents an Application Specific Instruction-set Processor (ASIP) for the SHA-3 BLAKE algorithm family by instruction set extensions (ISE) from an RISC (reduced instruction set computer) processor. With a design space exploration for this ASIP to increase the performance and reduce the area cost, we accomplish an efficient hardware and software implementation of BLAKE algorithm. The special instructions and their well-matched hardware function unit improve the calculation of the key section of the algorithm, namely G-functions. Also, relaxing the time constraint of the special function unit can decrease its hardware cost, while keeping the high data throughput of the processor. Evaluation results reveal the ASIP achieves 335 Mbps and 176 Mbps for BLAKE-256 and BLAKE-512. The extra area cost is only 8.06k equivalent gates. The proposed ASIP outperforms several software approaches on various platforms in cycle per byte. In fact, both high throughput and low hardware cost achieved by this programmable processor are comparable to that of ASIC implementations.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/transele.E95.C.1415/_p

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@ARTICLE{e95-c_8_1415,
author={Yuli ZHANG, Jun HAN, Xinqian WENG, Zhongzhu HE, Xiaoyang ZENG, },
journal={IEICE TRANSACTIONS on Electronics},
title={Design Approach and Implementation of Application Specific Instruction Set Processor for SHA-3 BLAKE Algorithm},
year={2012},
volume={E95-C},
number={8},
pages={1415-1426},
abstract={This paper presents an Application Specific Instruction-set Processor (ASIP) for the SHA-3 BLAKE algorithm family by instruction set extensions (ISE) from an RISC (reduced instruction set computer) processor. With a design space exploration for this ASIP to increase the performance and reduce the area cost, we accomplish an efficient hardware and software implementation of BLAKE algorithm. The special instructions and their well-matched hardware function unit improve the calculation of the key section of the algorithm, namely G-functions. Also, relaxing the time constraint of the special function unit can decrease its hardware cost, while keeping the high data throughput of the processor. Evaluation results reveal the ASIP achieves 335 Mbps and 176 Mbps for BLAKE-256 and BLAKE-512. The extra area cost is only 8.06k equivalent gates. The proposed ASIP outperforms several software approaches on various platforms in cycle per byte. In fact, both high throughput and low hardware cost achieved by this programmable processor are comparable to that of ASIC implementations.},
keywords={},
doi={10.1587/transele.E95.C.1415},
ISSN={1745-1353},
month={August},}

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TY - JOUR
TI - Design Approach and Implementation of Application Specific Instruction Set Processor for SHA-3 BLAKE Algorithm
T2 - IEICE TRANSACTIONS on Electronics
SP - 1415
EP - 1426
AU - Yuli ZHANG
AU - Jun HAN
AU - Xinqian WENG
AU - Zhongzhu HE
AU - Xiaoyang ZENG
PY - 2012
DO - 10.1587/transele.E95.C.1415
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E95-C
IS - 8
JA - IEICE TRANSACTIONS on Electronics
Y1 - August 2012
AB - This paper presents an Application Specific Instruction-set Processor (ASIP) for the SHA-3 BLAKE algorithm family by instruction set extensions (ISE) from an RISC (reduced instruction set computer) processor. With a design space exploration for this ASIP to increase the performance and reduce the area cost, we accomplish an efficient hardware and software implementation of BLAKE algorithm. The special instructions and their well-matched hardware function unit improve the calculation of the key section of the algorithm, namely G-functions. Also, relaxing the time constraint of the special function unit can decrease its hardware cost, while keeping the high data throughput of the processor. Evaluation results reveal the ASIP achieves 335 Mbps and 176 Mbps for BLAKE-256 and BLAKE-512. The extra area cost is only 8.06k equivalent gates. The proposed ASIP outperforms several software approaches on various platforms in cycle per byte. In fact, both high throughput and low hardware cost achieved by this programmable processor are comparable to that of ASIC implementations.
ER -