This paper investigates the effects of n-type doping in the emitter-base heterojunction vicinity on the DC and high-frequency characteristics of InP/InGaAs heterojunction bipolar transistors (HBTs). The n-type doping is shown to be very effective for enhancing the tunneling-injection current from the emitter and thus for reducing the collector-current turn-on voltage. However, it is also revealed that an unnecessary increase in the doping level only degrades the current gain, especially in the low-current region. A higher doping level also increases the emitter junction capacitance. The optimized HBT structures with a 0.5-µm-wide emitter exhibit turn-on voltage as low as 0.78 V and current gain of around 80 at J_C = 1 mA/µm². They also provide a current-gain cutoff frequency, f_t, of 280 GHz and a maximum oscillation frequency, f_max, of 385 GHz at V_CE = 1 V and J_C = 3 mA/µm². These results indicate that the proposed HBTs are very useful for high-speed and low-power IC applications.

This paper is a report on a high ESD breakdown-voltage InP HBT transimpedance amplifier IC for optical video distribution systems. To make ESD breakdown-voltage higher, we designed ESD protection circuits integrated in the TIA IC using base-collector/base-emitter diodes of InP HBTs and resistors. These components for ESD protection circuits have already existed in the employed InP HBT IC process, so no process modifications were needed. Furthermore, to meet requirements for use in optical video distribution systems, we studied circuit design techniques to obtain a good input-output linearity and a low-noise characteristic. Fabricated InP HBT TIA IC exhibited high human-body-model ESD breakdown voltages (±1000 V for power supply terminals, ±200 V for high-speed input/output terminals), good input-output linearity (less than 2.9-% duty-cycle-distortion), and low noise characteristic (10.7 pA/ averaged input-referred noise current density) with a -3-dB-down higher frequency of 6.9 GHz. To the best of our knowledge, this paper is the first literature describing InP ICs with high ESD-breakdown voltages.

With the aim of achieving heterogeneous integration of compound semiconductors with silicon technology, the fabrication of an InP/InGaAs transferred-substrate HBT (TS-HBT) on a Si substrate is reported. A current gain of 70 and a maximum current density of 12.3 mA/µm² were confirmed in a TS-HBT with a 340-nm-wide emitter. From microwave characteristics of the TS-HBT obtained after de-embedding, a cutoff frequency (f_T) of 510 GHz and a 26% reduction of the base-collector capacitance were estimated. However, the observed f_T was too high for an HBT with a 150-nm-thick collector. This discrepancy can be explained by the error in de-embedding, because an open pad is observed to have large capacitance and strong frequency dependence due to the conductivity of the Si substrate.

High output power AlGaN/GaN metal-insulator-semiconductor (MIS) hetero-junction field effect transistor (HFET) on Si substrate for millimeter-wave application has developed. High temperature chemical vapor deposition (HT-CVD) grown SiN as a gate insulator improves the breakdown characteristics which enables the operation at high drain voltage of 55 V. The device exhibits high drain current of 1.1 A/mm free from the current collapse and high RF gain of 10.4 dB. The amplifier module developed AlGaN/GaN MIS-HFET with the gate width of 5.4 mm exhibits an output power of 10.7 W and a linear gain of 4 dB at 26.5 GHz. The resultant high output power is very promising for long-distance communication at millimeter-wave in the future which would enable high speed and high density data transmission.

This paper describes high-temperature electron transport properties of AlGaN-channel HEMT fabricated on a free-standing AlN substrate, estimated at temperatures between 25 and 300. The AlGaN-channel HEMT exhibited significantly reduced temperature dependence in DC and RF device characteristics, as compared to those for the conventional AlGaN/GaN HEMT, resulting in larger values in both saturated drain current and current gain cutoff frequency at 300. Delay time analyses suggested that the temperature dependence of the AlGaN-channel HEMT was primarily dominated by the effective electron velocity in the AlGaN channel. These results indicate that an AlGaN-channel HEMT fabricated on an AlN substrate is promising for high-performance device applications at high temperatures.

We performed the (NH₄)₂S surface treatments before Al₂O₃ deposition to improve the Al₂O₃/_III-Nitride interface quality in Al₂O₃/AlGaN/GaN metal-oxide-semiconductor heterostructure field-effect transistors (MOSHFETs). Interface state density at the Al₂O₃/GaN interface was decreased by the (NH₄)₂S treatment. The hysteresis width in I_D-V_GS and g_m-V_GS characteristics of the Al₂O₃/AlGaN MOSHFETs with the (NH₄)₂S treatment was smaller than that without the (NH₄)₂S treatment. In addition, transconductance (g_m) decrease at a large gate voltage was relaxed by the (NH₄)₂S treatment. We also performed ultraviolet (UV) illumination during the (NH₄)₂S treatment for further improvement of the Al₂O₃/_III-Nitride interface quality. Interface state density of the Al₂O₃/GaN MOS diodes with the UV illumination was smaller than that without the UV illumination.

Current collapse of AlGaN/GaN heterostructure field-effect transistors (HFETs) formed on qualified epitaxial layers on Si substrates was successfully suppressed using graded field-plate (FP) structures. To improve the reproducibility of the FP structure manufacturing process, a simple process for linearly graded SiO₂ profile formation was developed. An HFET with a graded FP structure exhibited a significant decrease in an on-resistance increase ratio of 1.16 even after application of a drain bias of 600 V.

The design, fabrication and characterization of GaN based varactor diodes are presented. MOCVD was used for layer growth and the DC characteristic of 4 µm diameter diodes showed a turn-on voltage of 0.5 V, a breakdown voltage of 21 V and a modulation ratio of 1.63. High frequency characterization allowed obtaining the diode equivalent circuit and observed the bias dependence of the series resistance. The diode cutoff frequency was 900 GHz. A large-signal model was developed for the diode and the device power performance was evaluated. A power of 7.2 dBm with an efficiency of 16.6% was predicted for 47 GHz to 94 GHz doubling.

Novel thermopiles based on modulation doped AlGaAs/InGaAs and AlGaN/GaN heterostructures are proposed and developed for the first time, for uncooled infrared FPA (Focal Plane Array) image sensor application. The high responsivity with the high speed response time are designed to 4,900 V/W with 110 µs for AlGaAs/InGaAs, and to 460 V/W with 9 µs for AlGaN/GaN thermopiles, respectively. Based on integrated HEMT-MEMS technology, the AlGaAs/InGaAs 3232 matrix FPAs are fabricated to demonstrate its enhanced performances by black body measurement. The technology presented here demonstrates the potential of this approach for low-cost uncooled infrared FPA image sensor application.

A complete analysis of GaN-based structures with very promising characteristics for future optical waveguide devices, such as modulators, is presented. First the material growth was optimized for low dislocation density and surface roughness. Optical measurements demonstrate excellent waveguide properties in terms of index and temperature dependence while planar propagation losses are below 1 dB/cm. Bias was applied on both sides of the epitaxially grown films to evaluate the refractive index dependence on reverse voltage and a variation of 2.10^-3 was found for 30 V. These results support the possibility of using structures of this type for the fabrication of modulator devices such as Mach-Zehnder interferometers.

We report on the fabrication and analysis of basic digital circuits containing InAs nanowire transistors on a host substrate. The nanowires were assembled at predefined positions by means of electric field-assisted self-assembly within each run generating numerous circuits simultaneously. Inverter circuits composed of two separated nanowire transistors forming a driver and an active load have been fabricated. The inverter circuits exhibit a gain (>1) in the MHz regime and a time constant of about 0.9 ns. A sample & hold core element is fabricated based on an InAs nanowire transistor connected to a hold capacitor, both on a Silicon and an InP isolating substrate, respectively. The low leakage read-out of the hold capacitor is done by InP-based metal-insulator heterojunction FET grown on the same substrate prior to nanowire FET fabrication. Experimental operation of the circuit is demonstrated at 100 MHz sampling frequency. The presented approach enables III/V high-speed, low-voltage logic circuits on a wide variety of host substrates which may be up scaled to high volume circuits.

Large-signal-based nonlinear models are developed to analyze a variety of dynamic performances in a resonant tunneling diode (RTD) with peripheral circuits such as an integrated broad band bow-tie antenna, a bias circuit and a bias stabilizer circuit. Dynamic modes of the RTD are classified by the time-domain analysis with the model. On the basis of our model, we suggest a possibility to discuss a terahertz order oscillation mode control, and the ASK modulation in several tens Gbit/sec in the RTD with the broad band antenna. Validity of the model and analysis is shown by explaining measured results of modulated oscillation signals in fabricated triple-barrier RTDs.

The oscillators based on an active transmission line periodically loaded with RTD pairs are studied using circuit simulation with special attention to the behavior of harmonics. Generation of strong high order harmonic (9th) was observed. This is caused by the frequency locking in the high frequency passband. The harmonic oscillators based on this phenomenon are promising for high performance THz sources.

Ultra-wide band (UWB) pulse radar with high range resolution and dielectric permeability is promising as an internal imaging technique for non-destructive testing or breast cancer detection. Various imaging algorithms for buried objects within a dielectric medium have been proposed, such as aperture synthesis, the time reversal approach and the space-time beamforming algorithm. However, these algorithms mostly require a priori knowledge of the dielectric medium boundary in image focusing, and often suffer from inadequate accuracy to identify the detailed structure of buried targets, such as an edge or specular surface owing to employing the waveform focusing scheme. To overcome these difficulties, this paper proposes an accurate and non-parametric (i.e. using an arbitrary shape without target modeling) imaging algorithm for targets buried in a homogeneous dielectric medium by advancing the RPM (Range Points Migration) algorithm to internal imaging issues, which has been demonstrated to provide an accurate image even for complex-shaped objects in free-space measurement. Numerical simulations, including those for two-dimensional (2-D) and three-dimensional (3-D) cases, verify that the proposed algorithm enhances the imaging accuracy by less than 1/10 of the wavelength and significantly reduces the computational cost by specifying boundary extraction compared with the conventional SAR-based algorithm.

Electromagnetic scattering at high-frequencies is computationally heavy. Radar cross section (RCS) of electrically large concave and convex objects are solved by using the hybrid method. For convex and concave surfaces, Modified-Vector Physical Optics (MPO) with enhanced accuracy and Iterative Physical Optics (IPO) taking multiple-reflections into account, are selectively and independently applied for convex and concave parts of the scatterer. The accuracy of RCS by this hybrid method is tested with the MoM based simulator Wipl-D as the reference. The RCS from relatively small scatterers with the dimension of the order of a few wavelengths can be successfully predicted.

This paper presents a novel CMOS readout circuit for satellite infrared time delay and integration (TDI) arrays. An integrate-while-read method is adopted, and a dead-pixel-elimination circuit for solving a critical problem of the TDI scheme is integrated within a chip. In addition, an adaptive charge capacity control method is proposed to improve the signal-to-noise ratio (SNR) for low-temperature targets. The readout circuit was fabricated with a 0.35-µm CMOS process for a 5004 mid-wavelength infrared (MWIR) HgCdTe detector array. Using the circuit, a 90% background-limited infrared photodetection (BLIP) is satisfied over a wide input range (∼200–330 K), and the SNR is improved by 11 dB for the target temperature of 200 K.

This paper presents an Application Specific Instruction-set Processor (ASIP) for the SHA-3 BLAKE algorithm family by instruction set extensions (ISE) from an RISC (reduced instruction set computer) processor. With a design space exploration for this ASIP to increase the performance and reduce the area cost, we accomplish an efficient hardware and software implementation of BLAKE algorithm. The special instructions and their well-matched hardware function unit improve the calculation of the key section of the algorithm, namely G-functions. Also, relaxing the time constraint of the special function unit can decrease its hardware cost, while keeping the high data throughput of the processor. Evaluation results reveal the ASIP achieves 335 Mbps and 176 Mbps for BLAKE-256 and BLAKE-512. The extra area cost is only 8.06k equivalent gates. The proposed ASIP outperforms several software approaches on various platforms in cycle per byte. In fact, both high throughput and low hardware cost achieved by this programmable processor are comparable to that of ASIC implementations.

A low power and high performance with third order delta-sigma modulator for audio applications, fabricated in a 0.18 µm CMOS process, is presented. The modulator utilizes a third order noise shaping with only one opamp by using an opamp sharing technique. The opamp sharing among three integrator stages is achieved through the optimal operation timing, which makes use of the load capacitance differences between the three integrator stages. The designed modulator achieves 101.1 dB signal-to-noise ratio (A-weighted) and 101.5 dB dynamic range (A-weighted) with 7.5 mW power consumption from a 3.3 V supply. The die area is 1.27 mm². The fabricated delta-sigma modulator achieves the highest figure-of-merit among published high performance low power audio delta-sigma modulators.

This paper introduces a novel design method of an asynchronous pipeline based on dual-rail dynamic logic. The overhead of handshake control logic is greatly reduced by constructing a reliable critical datapath, which offers the pipeline high throughput as well as low power consumption. Synchronizing Logic Gates (SLGs), which have no data dependency problem, are used in the design to construct the reliable critical datapath. The design targets latch-free and extremely fine-grain or gate-level pipeline, where the depth of every pipeline stage is only one dual-rail dynamic logic. HSPICE simulation results, in a 65 nm design technology, indicate that the proposed design increases the throughput by 120% and decreases the power consumption by 54% compared with PS0, a classic dual-rail asynchronous pipeline implementation style, in 4-bit wide FIFOs. Moreover, this method is applied to design an array style multiplier. It shows that the proposed design reduces power by 37.9% compared to classic synchronous design when the workloads are 55%. A chip has been fabricated with a 44 multiplier function, which works well at 2.16G data-set/s (Post-layout simulation).

Reduction of the intensity noise in semiconductor lasers is an important subject for the higher performance of an application. Simultaneous usage of the superposition of high frequency current and the electric negative feedback loop was proposed to suppress the noise for the higher power operation of semiconductor lasers. Effective noise reduction of more than 25 dB with 80 mW operation was experimentally demonstrated.

A new clock gating circuit suitable for shift register is presented. The proposed clock gating circuit that consists of basic NOR gates is low power and small area. The power consumption of a 16-bit shift register implemented with the proposed clock gating circuit is about 66% lower than that found when using the conventional design.