Address Power Reduction Method for High-Resolution Plasma Display Panels Using Address Data Smoothing Based on a Visual Masking Effect

Masahiko SEKI; Masato FUJII; Tomokazu SHIGA

doi:10.1587/transele.E99.C.1277

Address Power Reduction Method for High-Resolution Plasma Display Panels Using Address Data Smoothing Based on a Visual Masking Effect

Masahiko SEKI, Masato FUJII, Tomokazu SHIGA

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This paper proposes an address power reduction method for plasma display panels (PDPs) using subfield data smoothing based on a visual masking effect. High-resolution, high-frame-rate PDPs have large address power loss caused by parasitic capacitance. Although the address power is reduced by smoothing the subfield data, noise is generated. The proposed method reduces the address power while maintaining the image quality by choosing the smoothing area of the address data based on the visual masking effect. The results of subjective assessment for the images based on smoothed address data indicate that image quality is maintained.

Publication: IEICE TRANSACTIONS on Electronics Vol.E99-C No.11 pp.1277-1282

Publication Date: 2016/11/01

Publicized

Online ISSN: 1745-1353

DOI: 10.1587/transele.E99.C.1277

Type of Manuscript: Special Section PAPER (Special Section on Electronic Displays)

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Authors

Masahiko SEKI
  The University of Electro-Communica-tions
Masato FUJII
  The University of Electro-Communica-tions
Tomokazu SHIGA
  The University of Electro-Communica-tions

Keyword

address power reduction, plasma display panel, visual masking effect

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Masahiko SEKI, Masato FUJII, Tomokazu SHIGA, "Address Power Reduction Method for High-Resolution Plasma Display Panels Using Address Data Smoothing Based on a Visual Masking Effect" in IEICE TRANSACTIONS on Electronics, vol. E99-C, no. 11, pp. 1277-1282, November 2016, doi: 10.1587/transele.E99.C.1277.
Abstract: This paper proposes an address power reduction method for plasma display panels (PDPs) using subfield data smoothing based on a visual masking effect. High-resolution, high-frame-rate PDPs have large address power loss caused by parasitic capacitance. Although the address power is reduced by smoothing the subfield data, noise is generated. The proposed method reduces the address power while maintaining the image quality by choosing the smoothing area of the address data based on the visual masking effect. The results of subjective assessment for the images based on smoothed address data indicate that image quality is maintained.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/transele.E99.C.1277/_p

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@ARTICLE{e99-c_11_1277,
author={Masahiko SEKI, Masato FUJII, Tomokazu SHIGA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Address Power Reduction Method for High-Resolution Plasma Display Panels Using Address Data Smoothing Based on a Visual Masking Effect},
year={2016},
volume={E99-C},
number={11},
pages={1277-1282},
abstract={This paper proposes an address power reduction method for plasma display panels (PDPs) using subfield data smoothing based on a visual masking effect. High-resolution, high-frame-rate PDPs have large address power loss caused by parasitic capacitance. Although the address power is reduced by smoothing the subfield data, noise is generated. The proposed method reduces the address power while maintaining the image quality by choosing the smoothing area of the address data based on the visual masking effect. The results of subjective assessment for the images based on smoothed address data indicate that image quality is maintained.},
keywords={},
doi={10.1587/transele.E99.C.1277},
ISSN={1745-1353},
month={November},}

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TY - JOUR
TI - Address Power Reduction Method for High-Resolution Plasma Display Panels Using Address Data Smoothing Based on a Visual Masking Effect
T2 - IEICE TRANSACTIONS on Electronics
SP - 1277
EP - 1282
AU - Masahiko SEKI
AU - Masato FUJII
AU - Tomokazu SHIGA
PY - 2016
DO - 10.1587/transele.E99.C.1277
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E99-C
IS - 11
JA - IEICE TRANSACTIONS on Electronics
Y1 - November 2016
AB - This paper proposes an address power reduction method for plasma display panels (PDPs) using subfield data smoothing based on a visual masking effect. High-resolution, high-frame-rate PDPs have large address power loss caused by parasitic capacitance. Although the address power is reduced by smoothing the subfield data, noise is generated. The proposed method reduces the address power while maintaining the image quality by choosing the smoothing area of the address data based on the visual masking effect. The results of subjective assessment for the images based on smoothed address data indicate that image quality is maintained.
ER -