A 9.35-ENOB, 14.8 fJ/conv.-step Fully-Passive Noise-Shaping SAR ADC

Zhijie CHEN; Masaya MIYAHARA; Akira MATSUZAWA

doi:10.1587/transele.E99.C.963

A 9.35-ENOB, 14.8 fJ/conv.-step Fully-Passive Noise-Shaping SAR ADC

Zhijie CHEN, Masaya MIYAHARA, Akira MATSUZAWA

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This paper proposes an opamp-free solution to implement single-phase-clock controlled noise shaping in a SAR ADC. Unlike a conventional noise shaping SAR ADC, the proposal realizes noise shaping by charge redistribution, which is a passive technique. The passive implementation has high power efficiency. Meanwhile, since the proposal maintains the basic architecture and operation method of a traditional SAR ADC, it retains all the advantages of a SAR ADC. Furthermore, noise shaping helps to improve the performance of SAR ADC and relaxes its non-ideal effects. Designed in a 65-nm CMOS technology, the prototype realizes 58-dB SNDR based on an 8-bit C-DAC at 50-MS/s sampling frequency. It consumes 120.7-µW power from a 0.8-V supply and achieves a FoM of 14.8-fJ per conversion step.

Publication: IEICE TRANSACTIONS on Electronics Vol.E99-C No.8 pp.963-973

Publication Date: 2016/08/01

Publicized

Online ISSN: 1745-1353

DOI: 10.1587/transele.E99.C.963

Type of Manuscript: PAPER

Category: Electronic Circuits

Authors

Zhijie CHEN
  Tokyo Institute of Technology
Masaya MIYAHARA
  Tokyo Institute of Technology
Akira MATSUZAWA
  Tokyo Institute of Technology

Keyword

fully passive noise shaping, charge-redistribution, SAR ADC, noise transfer function, zeros, poles

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Zhijie CHEN, Masaya MIYAHARA, Akira MATSUZAWA, "A 9.35-ENOB, 14.8 fJ/conv.-step Fully-Passive Noise-Shaping SAR ADC" in IEICE TRANSACTIONS on Electronics, vol. E99-C, no. 8, pp. 963-973, August 2016, doi: 10.1587/transele.E99.C.963.
Abstract: This paper proposes an opamp-free solution to implement single-phase-clock controlled noise shaping in a SAR ADC. Unlike a conventional noise shaping SAR ADC, the proposal realizes noise shaping by charge redistribution, which is a passive technique. The passive implementation has high power efficiency. Meanwhile, since the proposal maintains the basic architecture and operation method of a traditional SAR ADC, it retains all the advantages of a SAR ADC. Furthermore, noise shaping helps to improve the performance of SAR ADC and relaxes its non-ideal effects. Designed in a 65-nm CMOS technology, the prototype realizes 58-dB SNDR based on an 8-bit C-DAC at 50-MS/s sampling frequency. It consumes 120.7-µW power from a 0.8-V supply and achieves a FoM of 14.8-fJ per conversion step.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/transele.E99.C.963/_p

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@ARTICLE{e99-c_8_963,
author={Zhijie CHEN, Masaya MIYAHARA, Akira MATSUZAWA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 9.35-ENOB, 14.8 fJ/conv.-step Fully-Passive Noise-Shaping SAR ADC},
year={2016},
volume={E99-C},
number={8},
pages={963-973},
abstract={This paper proposes an opamp-free solution to implement single-phase-clock controlled noise shaping in a SAR ADC. Unlike a conventional noise shaping SAR ADC, the proposal realizes noise shaping by charge redistribution, which is a passive technique. The passive implementation has high power efficiency. Meanwhile, since the proposal maintains the basic architecture and operation method of a traditional SAR ADC, it retains all the advantages of a SAR ADC. Furthermore, noise shaping helps to improve the performance of SAR ADC and relaxes its non-ideal effects. Designed in a 65-nm CMOS technology, the prototype realizes 58-dB SNDR based on an 8-bit C-DAC at 50-MS/s sampling frequency. It consumes 120.7-µW power from a 0.8-V supply and achieves a FoM of 14.8-fJ per conversion step.},
keywords={},
doi={10.1587/transele.E99.C.963},
ISSN={1745-1353},
month={August},}

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TY - JOUR
TI - A 9.35-ENOB, 14.8 fJ/conv.-step Fully-Passive Noise-Shaping SAR ADC
T2 - IEICE TRANSACTIONS on Electronics
SP - 963
EP - 973
AU - Zhijie CHEN
AU - Masaya MIYAHARA
AU - Akira MATSUZAWA
PY - 2016
DO - 10.1587/transele.E99.C.963
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E99-C
IS - 8
JA - IEICE TRANSACTIONS on Electronics
Y1 - August 2016
AB - This paper proposes an opamp-free solution to implement single-phase-clock controlled noise shaping in a SAR ADC. Unlike a conventional noise shaping SAR ADC, the proposal realizes noise shaping by charge redistribution, which is a passive technique. The passive implementation has high power efficiency. Meanwhile, since the proposal maintains the basic architecture and operation method of a traditional SAR ADC, it retains all the advantages of a SAR ADC. Furthermore, noise shaping helps to improve the performance of SAR ADC and relaxes its non-ideal effects. Designed in a 65-nm CMOS technology, the prototype realizes 58-dB SNDR based on an 8-bit C-DAC at 50-MS/s sampling frequency. It consumes 120.7-µW power from a 0.8-V supply and achieves a FoM of 14.8-fJ per conversion step.
ER -