This paper discusses non-ideal issues in a fully passive noise shaping successive approximation register analog-to-digital converter. The fully passive noise shaping techniques are realized by switches and capacitors without operational amplifiers to be scalable and power efficient. However, some non-ideal issues, such as parasitic capacitance, comparator noise, thermal noise, will affect the performance of the noise shaping and then degrade the final achievable resolution. This paper analyzes the effects of the main non-ideal issues and provides the design reference for fully passive noise shaping techniques. The analysis is based on 2nd order fully passive noise shaping SAR ADC with an 8-bit architecture and an OSR of 4.

This paper proposes an opamp-free solution to implement single-phase-clock controlled noise shaping in a SAR ADC. Unlike a conventional noise shaping SAR ADC, the proposal realizes noise shaping by charge redistribution, which is a passive technique. The passive implementation has high power efficiency. Meanwhile, since the proposal maintains the basic architecture and operation method of a traditional SAR ADC, it retains all the advantages of a SAR ADC. Furthermore, noise shaping helps to improve the performance of SAR ADC and relaxes its non-ideal effects. Designed in a 65-nm CMOS technology, the prototype realizes 58-dB SNDR based on an 8-bit C-DAC at 50-MS/s sampling frequency. It consumes 120.7-µW power from a 0.8-V supply and achieves a FoM of 14.8-fJ per conversion step.

This paper analyzes three passive noise shaping techniques in a SAR ADC. These passive noise shaping techniques can realize 1st and 2nd order noise shaping. These proposed opamp-less noise shaping techniques are realized by charge-redistribution. This means that the proposals maintain the basic architecture and operation principle of a charge-redistribution SAR ADC. Since the proposed techniques work in a passive mode, the proposals have high power efficiency. Meanwhile, the proposed noise shaping SAR ADCs are robust to feature size scaling and power supply reduction. Flicker noise is not introduced into the ADC by passive noise shaping techniques. Therefore, no additional calibration techniques for flicker noise are required. The noise shaping effects of the 1st and 2nd order noise shaping are verified by behavioral simulation results. The relationship between resolution improvement and oversampling rate is also explored in this paper.

This paper describes the design of a small-offset 12-bit CMOS charge-redistribution DAC using a weighted-mean flip-around sample-and-hold circuit (S/H). Flip-around S/H topology can realize small-offset characteristics, and it is effective to reduce power dissipation and chip area because independent feedback capacitors are not necessary. In this DAC the small-offset characteristic remains not only in amplification phase but also in sampling phase with the circuit technique. The design of 1.8 V, 50 MS/s fully differential DAC with output swing of 2 Vp-p has very small offset of 100 µV for the reset switch mismatch of 2%. A technique to improve dynamic performance measured by SFDR using damping resistors and switches at the output stage is also presented. The designed 12-bit DAC with 0.25 µm CMOS technology has low-power dissipation of 35 mW at 50 MS/s.