Timing optimization is an important goal of global routing in deep submicron era. To guarantee the timing performance of the circuit, merely adopting topology optimization becomes inadequate. In this paper, we present an efficient timing-driven global routing algorithm with buffer insertion. Our approach is capable of applying topological-based timing optimization and buffer insertion simultaneously with routablity considerations. Compared with previous works, we efficiently solve the timing issues under a limited buffer usage. The experimental results have demonstrated significant delay improvement within short runtime with very small number of buffers inserted.
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Jingyu XU, Xianlong HONG, Tong JING, "Timing-Driven Global Routing with Efficient Buffer Insertion" in IEICE TRANSACTIONS on Fundamentals,
vol. E88-A, no. 11, pp. 3188-3195, November 2005, doi: 10.1093/ietfec/e88-a.11.3188.
Abstract: Timing optimization is an important goal of global routing in deep submicron era. To guarantee the timing performance of the circuit, merely adopting topology optimization becomes inadequate. In this paper, we present an efficient timing-driven global routing algorithm with buffer insertion. Our approach is capable of applying topological-based timing optimization and buffer insertion simultaneously with routablity considerations. Compared with previous works, we efficiently solve the timing issues under a limited buffer usage. The experimental results have demonstrated significant delay improvement within short runtime with very small number of buffers inserted.
URL: https://globals.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e88-a.11.3188/_p
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@ARTICLE{e88-a_11_3188,
author={Jingyu XU, Xianlong HONG, Tong JING, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Timing-Driven Global Routing with Efficient Buffer Insertion},
year={2005},
volume={E88-A},
number={11},
pages={3188-3195},
abstract={Timing optimization is an important goal of global routing in deep submicron era. To guarantee the timing performance of the circuit, merely adopting topology optimization becomes inadequate. In this paper, we present an efficient timing-driven global routing algorithm with buffer insertion. Our approach is capable of applying topological-based timing optimization and buffer insertion simultaneously with routablity considerations. Compared with previous works, we efficiently solve the timing issues under a limited buffer usage. The experimental results have demonstrated significant delay improvement within short runtime with very small number of buffers inserted.},
keywords={},
doi={10.1093/ietfec/e88-a.11.3188},
ISSN={},
month={November},}
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TY - JOUR
TI - Timing-Driven Global Routing with Efficient Buffer Insertion
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 3188
EP - 3195
AU - Jingyu XU
AU - Xianlong HONG
AU - Tong JING
PY - 2005
DO - 10.1093/ietfec/e88-a.11.3188
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E88-A
IS - 11
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - November 2005
AB - Timing optimization is an important goal of global routing in deep submicron era. To guarantee the timing performance of the circuit, merely adopting topology optimization becomes inadequate. In this paper, we present an efficient timing-driven global routing algorithm with buffer insertion. Our approach is capable of applying topological-based timing optimization and buffer insertion simultaneously with routablity considerations. Compared with previous works, we efficiently solve the timing issues under a limited buffer usage. The experimental results have demonstrated significant delay improvement within short runtime with very small number of buffers inserted.
ER -