Hardware Oriented Low-Complexity Intra Coding Algorithm for SHVC

Takafumi KATAYAMA; Tian SONG; Wen SHI; Gen FUJITA; Xiantao JIANG; Takashi SHIMAMOTO

doi:10.1587/transfun.E100.A.2936

Hardware Oriented Low-Complexity Intra Coding Algorithm for SHVC

Takafumi KATAYAMA, Tian SONG, Wen SHI, Gen FUJITA, Xiantao JIANG, Takashi SHIMAMOTO

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Scalable high efficiency video coding (SHVC) can provide variable video quality according to terminal devices. However, the computational complexity of SHVC is increased by introducing new techniques based on high efficiency video coding (HEVC). In this paper, a hardware oriented low complexity algorithm is proposed. The hardware oriented proposals have two key points. Firstly, the coding unit depth is determined by analyzing the boundary correlation between coding units before encoding process starts. Secondly, the redundant calculation of R-D optimization is reduced by adaptively using the information of the neighboring coding units and the co-located units in the base layer. The simulation results show that the proposed algorithm can achieve over 62% computation complexity reduction compared to the original SHM11.0. Compared with other related work, over 11% time saving have been achieved without PSNR loss. Furthermore, the proposed algorithm is hardware friendly which can be implemented in a small area.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E100-A No.12 pp.2936-2947

Publication Date: 2017/12/01

Publicized

Online ISSN: 1745-1337

DOI: 10.1587/transfun.E100.A.2936

Type of Manuscript: PAPER

Category: Digital Signal Processing

Authors

Takafumi KATAYAMA
  The University of Tokushima
Tian SONG
  The University of Tokushima
Wen SHI
  The University of Tokushima
Gen FUJITA
  Osaka Electro-Communication University
Xiantao JIANG
  The University of Tokushima
Takashi SHIMAMOTO
  The University of Tokushima

Keyword

high efficiency video coding (HEVC), scalable high efficiency video coding (SHVC), inter layer reference prediction, intra prediction

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Takafumi KATAYAMA, Tian SONG, Wen SHI, Gen FUJITA, Xiantao JIANG, Takashi SHIMAMOTO, "Hardware Oriented Low-Complexity Intra Coding Algorithm for SHVC" in IEICE TRANSACTIONS on Fundamentals, vol. E100-A, no. 12, pp. 2936-2947, December 2017, doi: 10.1587/transfun.E100.A.2936.
Abstract: Scalable high efficiency video coding (SHVC) can provide variable video quality according to terminal devices. However, the computational complexity of SHVC is increased by introducing new techniques based on high efficiency video coding (HEVC). In this paper, a hardware oriented low complexity algorithm is proposed. The hardware oriented proposals have two key points. Firstly, the coding unit depth is determined by analyzing the boundary correlation between coding units before encoding process starts. Secondly, the redundant calculation of R-D optimization is reduced by adaptively using the information of the neighboring coding units and the co-located units in the base layer. The simulation results show that the proposed algorithm can achieve over 62% computation complexity reduction compared to the original SHM11.0. Compared with other related work, over 11% time saving have been achieved without PSNR loss. Furthermore, the proposed algorithm is hardware friendly which can be implemented in a small area.
URL: https://globals.ieice.org/en_transactions/fundamentals/10.1587/transfun.E100.A.2936/_p

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@ARTICLE{e100-a_12_2936,
author={Takafumi KATAYAMA, Tian SONG, Wen SHI, Gen FUJITA, Xiantao JIANG, Takashi SHIMAMOTO, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Hardware Oriented Low-Complexity Intra Coding Algorithm for SHVC},
year={2017},
volume={E100-A},
number={12},
pages={2936-2947},
abstract={Scalable high efficiency video coding (SHVC) can provide variable video quality according to terminal devices. However, the computational complexity of SHVC is increased by introducing new techniques based on high efficiency video coding (HEVC). In this paper, a hardware oriented low complexity algorithm is proposed. The hardware oriented proposals have two key points. Firstly, the coding unit depth is determined by analyzing the boundary correlation between coding units before encoding process starts. Secondly, the redundant calculation of R-D optimization is reduced by adaptively using the information of the neighboring coding units and the co-located units in the base layer. The simulation results show that the proposed algorithm can achieve over 62% computation complexity reduction compared to the original SHM11.0. Compared with other related work, over 11% time saving have been achieved without PSNR loss. Furthermore, the proposed algorithm is hardware friendly which can be implemented in a small area.},
keywords={},
doi={10.1587/transfun.E100.A.2936},
ISSN={1745-1337},
month={December},}

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TY - JOUR
TI - Hardware Oriented Low-Complexity Intra Coding Algorithm for SHVC
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2936
EP - 2947
AU - Takafumi KATAYAMA
AU - Tian SONG
AU - Wen SHI
AU - Gen FUJITA
AU - Xiantao JIANG
AU - Takashi SHIMAMOTO
PY - 2017
DO - 10.1587/transfun.E100.A.2936
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E100-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2017
AB - Scalable high efficiency video coding (SHVC) can provide variable video quality according to terminal devices. However, the computational complexity of SHVC is increased by introducing new techniques based on high efficiency video coding (HEVC). In this paper, a hardware oriented low complexity algorithm is proposed. The hardware oriented proposals have two key points. Firstly, the coding unit depth is determined by analyzing the boundary correlation between coding units before encoding process starts. Secondly, the redundant calculation of R-D optimization is reduced by adaptively using the information of the neighboring coding units and the co-located units in the base layer. The simulation results show that the proposed algorithm can achieve over 62% computation complexity reduction compared to the original SHM11.0. Compared with other related work, over 11% time saving have been achieved without PSNR loss. Furthermore, the proposed algorithm is hardware friendly which can be implemented in a small area.
ER -