Fault-Injection Analysis to Estimate SEU Failure in Time by Using Frame-Based Partial Reconfiguration

Yoshihiro ICHINOMIYA; Tsuyoshi KIMURA; Motoki AMAGASAKI; Morihiro KUGA; Masahiro IIDA; Toshinori SUEYOSHI

doi:10.1587/transfun.E95.A.2347

Fault-Injection Analysis to Estimate SEU Failure in Time by Using Frame-Based Partial Reconfiguration

Yoshihiro ICHINOMIYA, Tsuyoshi KIMURA, Motoki AMAGASAKI, Morihiro KUGA, Masahiro IIDA, Toshinori SUEYOSHI

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SRAM-based field programmable gate arrays (FPGAs) are vulnerable to a soft-error induced by radiation. Techniques for designing dependable circuits, such as triple modular redundancy (TMR) with scrubbing, have been studied extensively. However, currently available evaluation techniques that can be used to check the dependability of these circuits are inadequate. Further, their results are restrictive because they do not represent the result in terms of general reliability indicator to decide whether the circuit is dependable. In this paper, we propose an evaluation method that provides results in terms of the realistic failure in time (FIT) by using reconfiguration-based fault-injection analysis. Current fault-injection analyses do not consider fault accumulation, and hence, they are not suitable for evaluating the dependability of a circuit such as a TMR circuit. Therefore, we configure an evaluation system that can handle fault-accumulation by using frame-based partial reconfiguration and the bootstrap method. By using the proposed method, we successfully evaluated a TMR circuit and could discuss the result in terms of realistic FIT data. Our method can evaluate the dependability of an actual system, and help with the tuning and selection in dependable system design.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E95-A No.12 pp.2347-2356

Publication Date: 2012/12/01

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Online ISSN: 1745-1337

DOI: 10.1587/transfun.E95.A.2347

Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)

Category: High-Level Synthesis and System-Level Design

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Yoshihiro ICHINOMIYA, Tsuyoshi KIMURA, Motoki AMAGASAKI, Morihiro KUGA, Masahiro IIDA, Toshinori SUEYOSHI, "Fault-Injection Analysis to Estimate SEU Failure in Time by Using Frame-Based Partial Reconfiguration" in IEICE TRANSACTIONS on Fundamentals, vol. E95-A, no. 12, pp. 2347-2356, December 2012, doi: 10.1587/transfun.E95.A.2347.
Abstract: SRAM-based field programmable gate arrays (FPGAs) are vulnerable to a soft-error induced by radiation. Techniques for designing dependable circuits, such as triple modular redundancy (TMR) with scrubbing, have been studied extensively. However, currently available evaluation techniques that can be used to check the dependability of these circuits are inadequate. Further, their results are restrictive because they do not represent the result in terms of general reliability indicator to decide whether the circuit is dependable. In this paper, we propose an evaluation method that provides results in terms of the realistic failure in time (FIT) by using reconfiguration-based fault-injection analysis. Current fault-injection analyses do not consider fault accumulation, and hence, they are not suitable for evaluating the dependability of a circuit such as a TMR circuit. Therefore, we configure an evaluation system that can handle fault-accumulation by using frame-based partial reconfiguration and the bootstrap method. By using the proposed method, we successfully evaluated a TMR circuit and could discuss the result in terms of realistic FIT data. Our method can evaluate the dependability of an actual system, and help with the tuning and selection in dependable system design.
URL: https://globals.ieice.org/en_transactions/fundamentals/10.1587/transfun.E95.A.2347/_p

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@ARTICLE{e95-a_12_2347,
author={Yoshihiro ICHINOMIYA, Tsuyoshi KIMURA, Motoki AMAGASAKI, Morihiro KUGA, Masahiro IIDA, Toshinori SUEYOSHI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Fault-Injection Analysis to Estimate SEU Failure in Time by Using Frame-Based Partial Reconfiguration},
year={2012},
volume={E95-A},
number={12},
pages={2347-2356},
abstract={SRAM-based field programmable gate arrays (FPGAs) are vulnerable to a soft-error induced by radiation. Techniques for designing dependable circuits, such as triple modular redundancy (TMR) with scrubbing, have been studied extensively. However, currently available evaluation techniques that can be used to check the dependability of these circuits are inadequate. Further, their results are restrictive because they do not represent the result in terms of general reliability indicator to decide whether the circuit is dependable. In this paper, we propose an evaluation method that provides results in terms of the realistic failure in time (FIT) by using reconfiguration-based fault-injection analysis. Current fault-injection analyses do not consider fault accumulation, and hence, they are not suitable for evaluating the dependability of a circuit such as a TMR circuit. Therefore, we configure an evaluation system that can handle fault-accumulation by using frame-based partial reconfiguration and the bootstrap method. By using the proposed method, we successfully evaluated a TMR circuit and could discuss the result in terms of realistic FIT data. Our method can evaluate the dependability of an actual system, and help with the tuning and selection in dependable system design.},
keywords={},
doi={10.1587/transfun.E95.A.2347},
ISSN={1745-1337},
month={December},}

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TY - JOUR
TI - Fault-Injection Analysis to Estimate SEU Failure in Time by Using Frame-Based Partial Reconfiguration
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2347
EP - 2356
AU - Yoshihiro ICHINOMIYA
AU - Tsuyoshi KIMURA
AU - Motoki AMAGASAKI
AU - Morihiro KUGA
AU - Masahiro IIDA
AU - Toshinori SUEYOSHI
PY - 2012
DO - 10.1587/transfun.E95.A.2347
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E95-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2012
AB - SRAM-based field programmable gate arrays (FPGAs) are vulnerable to a soft-error induced by radiation. Techniques for designing dependable circuits, such as triple modular redundancy (TMR) with scrubbing, have been studied extensively. However, currently available evaluation techniques that can be used to check the dependability of these circuits are inadequate. Further, their results are restrictive because they do not represent the result in terms of general reliability indicator to decide whether the circuit is dependable. In this paper, we propose an evaluation method that provides results in terms of the realistic failure in time (FIT) by using reconfiguration-based fault-injection analysis. Current fault-injection analyses do not consider fault accumulation, and hence, they are not suitable for evaluating the dependability of a circuit such as a TMR circuit. Therefore, we configure an evaluation system that can handle fault-accumulation by using frame-based partial reconfiguration and the bootstrap method. By using the proposed method, we successfully evaluated a TMR circuit and could discuss the result in terms of realistic FIT data. Our method can evaluate the dependability of an actual system, and help with the tuning and selection in dependable system design.
ER -