A 12-bit Interpolated Pipeline ADC Using Body Voltage Controlled Amplifier

Hyunui LEE; Masaya MIYAHARA; Akira MATSUZAWA

doi:10.1587/transfun.E96.A.2508

A 12-bit Interpolated Pipeline ADC Using Body Voltage Controlled Amplifier

Hyunui LEE, Masaya MIYAHARA, Akira MATSUZAWA

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This paper presents a 12-bit interpolated pipeline analog to digital converter (ADC) using body voltage controlled amplifier for current biasing and common mode feedback (CMFB). The proposed body voltage control method allows the amplifier to achieve small power consumption and large output swing. The proposed amplifier has a power consumption lower than 15.6mW, almost half of the folded cascode amplifier satisfying 12-bit, 400MS/s ADC operation. Moreover, the proposed amplifier secures 600mV output swing, which is one drain source voltage (V_DS) wider compared with the telescopic amplifier. The 12-bit interpolated pipeline ADC using the proposed amplifier is fabricated in a 1P9M 90nm CMOS technology with a 1.2V supply voltage. The ADC achieves an effective number of bit (ENOB) of about 10-bit at 300MS/s and an figure of merit (FoM) of 0.2pJ/conv. when the frequency of the input signal is sufficiently low.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E96-A No.12 pp.2508-2515

Publication Date: 2013/12/01

Publicized

Online ISSN: 1745-1337

DOI: 10.1587/transfun.E96.A.2508

Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)

Category: Circuit Design

Authors

Hyunui LEE
  Tokyo Institute of Technology
Masaya MIYAHARA
  Tokyo Institute of Technology
Akira MATSUZAWA
  Tokyo Institute of Technology

Keyword

analog-to-digital converter, interpolated pipeline topology, amplifier, body voltage control technique

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Hyunui LEE, Masaya MIYAHARA, Akira MATSUZAWA, "A 12-bit Interpolated Pipeline ADC Using Body Voltage Controlled Amplifier" in IEICE TRANSACTIONS on Fundamentals, vol. E96-A, no. 12, pp. 2508-2515, December 2013, doi: 10.1587/transfun.E96.A.2508.
Abstract: This paper presents a 12-bit interpolated pipeline analog to digital converter (ADC) using body voltage controlled amplifier for current biasing and common mode feedback (CMFB). The proposed body voltage control method allows the amplifier to achieve small power consumption and large output swing. The proposed amplifier has a power consumption lower than 15.6mW, almost half of the folded cascode amplifier satisfying 12-bit, 400MS/s ADC operation. Moreover, the proposed amplifier secures 600mV output swing, which is one drain source voltage (V_DS) wider compared with the telescopic amplifier. The 12-bit interpolated pipeline ADC using the proposed amplifier is fabricated in a 1P9M 90nm CMOS technology with a 1.2V supply voltage. The ADC achieves an effective number of bit (ENOB) of about 10-bit at 300MS/s and an figure of merit (FoM) of 0.2pJ/conv. when the frequency of the input signal is sufficiently low.
URL: https://globals.ieice.org/en_transactions/fundamentals/10.1587/transfun.E96.A.2508/_p

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@ARTICLE{e96-a_12_2508,
author={Hyunui LEE, Masaya MIYAHARA, Akira MATSUZAWA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A 12-bit Interpolated Pipeline ADC Using Body Voltage Controlled Amplifier},
year={2013},
volume={E96-A},
number={12},
pages={2508-2515},
abstract={This paper presents a 12-bit interpolated pipeline analog to digital converter (ADC) using body voltage controlled amplifier for current biasing and common mode feedback (CMFB). The proposed body voltage control method allows the amplifier to achieve small power consumption and large output swing. The proposed amplifier has a power consumption lower than 15.6mW, almost half of the folded cascode amplifier satisfying 12-bit, 400MS/s ADC operation. Moreover, the proposed amplifier secures 600mV output swing, which is one drain source voltage (V_DS) wider compared with the telescopic amplifier. The 12-bit interpolated pipeline ADC using the proposed amplifier is fabricated in a 1P9M 90nm CMOS technology with a 1.2V supply voltage. The ADC achieves an effective number of bit (ENOB) of about 10-bit at 300MS/s and an figure of merit (FoM) of 0.2pJ/conv. when the frequency of the input signal is sufficiently low.},
keywords={},
doi={10.1587/transfun.E96.A.2508},
ISSN={1745-1337},
month={December},}

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TY - JOUR
TI - A 12-bit Interpolated Pipeline ADC Using Body Voltage Controlled Amplifier
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2508
EP - 2515
AU - Hyunui LEE
AU - Masaya MIYAHARA
AU - Akira MATSUZAWA
PY - 2013
DO - 10.1587/transfun.E96.A.2508
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E96-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2013
AB - This paper presents a 12-bit interpolated pipeline analog to digital converter (ADC) using body voltage controlled amplifier for current biasing and common mode feedback (CMFB). The proposed body voltage control method allows the amplifier to achieve small power consumption and large output swing. The proposed amplifier has a power consumption lower than 15.6mW, almost half of the folded cascode amplifier satisfying 12-bit, 400MS/s ADC operation. Moreover, the proposed amplifier secures 600mV output swing, which is one drain source voltage (V_DS) wider compared with the telescopic amplifier. The 12-bit interpolated pipeline ADC using the proposed amplifier is fabricated in a 1P9M 90nm CMOS technology with a 1.2V supply voltage. The ADC achieves an effective number of bit (ENOB) of about 10-bit at 300MS/s and an figure of merit (FoM) of 0.2pJ/conv. when the frequency of the input signal is sufficiently low.
ER -