A 6 bit, 7 mW, 700 MS/s Subranging ADC Using CDAC and Gate-Weighted Interpolation

Hyunui LEE; Yusuke ASADA; Masaya MIYAHARA; Akira MATSUZAWA

doi:10.1587/transfun.E96.A.422

A 6 bit, 7 mW, 700 MS/s Subranging ADC Using CDAC and Gate-Weighted Interpolation

Hyunui LEE, Yusuke ASADA, Masaya MIYAHARA, Akira MATSUZAWA

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A 6-bit, 7 mW, 700 MS/s subranging ADC using Capacitive DAC (CDAC) and gate-weighted interpolation fabricated in 90 nm CMOS technology is demonstrated. CDACs are used as a reference selection circuit instead of resistive DACs (RDAC) for reducing settling time and power dissipation. A gate-weighted interpolation scheme is also incorporated to the comparators, to reduce the circuit components, power dissipation and mismatch of conversion stages. By virtue of recent technology scaling, an interpolation can be realized in the saturation region with small error. A digital offset calibration technique using capacitor reduces comparator's offset voltage from 10 mV to 1.5 mV per sigma. Experimental results show that the proposed ADC achieves a SNDR of 34 dB with calibration and FoM is 250 fJ/conv., which is very attractive as an embedded IP for low power SoCs.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E96-A No.2 pp.422-433

Publication Date: 2013/02/01

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Online ISSN: 1745-1337

DOI: 10.1587/transfun.E96.A.422

Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)

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Hyunui LEE, Yusuke ASADA, Masaya MIYAHARA, Akira MATSUZAWA, "A 6 bit, 7 mW, 700 MS/s Subranging ADC Using CDAC and Gate-Weighted Interpolation" in IEICE TRANSACTIONS on Fundamentals, vol. E96-A, no. 2, pp. 422-433, February 2013, doi: 10.1587/transfun.E96.A.422.
Abstract: A 6-bit, 7 mW, 700 MS/s subranging ADC using Capacitive DAC (CDAC) and gate-weighted interpolation fabricated in 90 nm CMOS technology is demonstrated. CDACs are used as a reference selection circuit instead of resistive DACs (RDAC) for reducing settling time and power dissipation. A gate-weighted interpolation scheme is also incorporated to the comparators, to reduce the circuit components, power dissipation and mismatch of conversion stages. By virtue of recent technology scaling, an interpolation can be realized in the saturation region with small error. A digital offset calibration technique using capacitor reduces comparator's offset voltage from 10 mV to 1.5 mV per sigma. Experimental results show that the proposed ADC achieves a SNDR of 34 dB with calibration and FoM is 250 fJ/conv., which is very attractive as an embedded IP for low power SoCs.
URL: https://globals.ieice.org/en_transactions/fundamentals/10.1587/transfun.E96.A.422/_p

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@ARTICLE{e96-a_2_422,
author={Hyunui LEE, Yusuke ASADA, Masaya MIYAHARA, Akira MATSUZAWA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A 6 bit, 7 mW, 700 MS/s Subranging ADC Using CDAC and Gate-Weighted Interpolation},
year={2013},
volume={E96-A},
number={2},
pages={422-433},
abstract={A 6-bit, 7 mW, 700 MS/s subranging ADC using Capacitive DAC (CDAC) and gate-weighted interpolation fabricated in 90 nm CMOS technology is demonstrated. CDACs are used as a reference selection circuit instead of resistive DACs (RDAC) for reducing settling time and power dissipation. A gate-weighted interpolation scheme is also incorporated to the comparators, to reduce the circuit components, power dissipation and mismatch of conversion stages. By virtue of recent technology scaling, an interpolation can be realized in the saturation region with small error. A digital offset calibration technique using capacitor reduces comparator's offset voltage from 10 mV to 1.5 mV per sigma. Experimental results show that the proposed ADC achieves a SNDR of 34 dB with calibration and FoM is 250 fJ/conv., which is very attractive as an embedded IP for low power SoCs.},
keywords={},
doi={10.1587/transfun.E96.A.422},
ISSN={1745-1337},
month={February},}

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TY - JOUR
TI - A 6 bit, 7 mW, 700 MS/s Subranging ADC Using CDAC and Gate-Weighted Interpolation
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 422
EP - 433
AU - Hyunui LEE
AU - Yusuke ASADA
AU - Masaya MIYAHARA
AU - Akira MATSUZAWA
PY - 2013
DO - 10.1587/transfun.E96.A.422
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E96-A
IS - 2
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - February 2013
AB - A 6-bit, 7 mW, 700 MS/s subranging ADC using Capacitive DAC (CDAC) and gate-weighted interpolation fabricated in 90 nm CMOS technology is demonstrated. CDACs are used as a reference selection circuit instead of resistive DACs (RDAC) for reducing settling time and power dissipation. A gate-weighted interpolation scheme is also incorporated to the comparators, to reduce the circuit components, power dissipation and mismatch of conversion stages. By virtue of recent technology scaling, an interpolation can be realized in the saturation region with small error. A digital offset calibration technique using capacitor reduces comparator's offset voltage from 10 mV to 1.5 mV per sigma. Experimental results show that the proposed ADC achieves a SNDR of 34 dB with calibration and FoM is 250 fJ/conv., which is very attractive as an embedded IP for low power SoCs.
ER -