A Design of Op-Amp Free SAR-VCO Hybrid ADC with 2<SUP>nd</SUP>-Order Noise Shaping in 65nm CMOS Technology

Yu HOU; Zhijie CHEN; Masaya MIYAHARA; Akira MATSUZAWA

doi:10.1587/transfun.E99.A.2473

A Design of Op-Amp Free SAR-VCO Hybrid ADC with 2^nd-Order Noise Shaping in 65nm CMOS Technology

Yu HOU, Zhijie CHEN, Masaya MIYAHARA, Akira MATSUZAWA

Full Text Views

0

Share
Cite this

Summary :

This paper proposes a SAR-VCO hybrid 1-1 MASH ADC architecture, where a fully-passive 1^st-order noise-shaping SAR ADC is implemented in the first stage to eliminate Op-amp. A VCO-based ADC quantizes the residue of the SAR ADC with one additional order of noise shaping in the second stage. The inter-stage gain error can be suppressed by a foreground calibration technique. The proposed ADC architecture is expected to accomplish 2^nd-order noise shaping without Op-amp, which makes both high SNDR and low power possible. A prototype ADC is designed in a 65nm CMOS technology to verify the feasibility of the proposed ADC architecture. The transistor-level simulation results show that 75.7dB SNDR is achieved in 5MHz bandwidth at 60MS/s. The power consumption is 748.9µW under 1.0V supply, which results in a FoM of 14.9fJ/conversion-step.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E99-A No.12 pp.2473-2482

Publication Date: 2016/12/01

Publicized

Online ISSN: 1745-1337

DOI: 10.1587/transfun.E99.A.2473

Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)

Category

Authors

Yu HOU
  Tokyo Institute of Technology
Zhijie CHEN
  Tokyo Institute of Technology
Masaya MIYAHARA
  Tokyo Institute of Technology
Akira MATSUZAWA
  Tokyo Institute of Technology

Keyword

Op-amp free, SAR, VCO, hybrid, 1-1 MASH ADC

Cite this

Copy

Yu HOU, Zhijie CHEN, Masaya MIYAHARA, Akira MATSUZAWA, "A Design of Op-Amp Free SAR-VCO Hybrid ADC with 2nd-Order Noise Shaping in 65nm CMOS Technology" in IEICE TRANSACTIONS on Fundamentals, vol. E99-A, no. 12, pp. 2473-2482, December 2016, doi: 10.1587/transfun.E99.A.2473.
Abstract: This paper proposes a SAR-VCO hybrid 1-1 MASH ADC architecture, where a fully-passive 1^st-order noise-shaping SAR ADC is implemented in the first stage to eliminate Op-amp. A VCO-based ADC quantizes the residue of the SAR ADC with one additional order of noise shaping in the second stage. The inter-stage gain error can be suppressed by a foreground calibration technique. The proposed ADC architecture is expected to accomplish 2^nd-order noise shaping without Op-amp, which makes both high SNDR and low power possible. A prototype ADC is designed in a 65nm CMOS technology to verify the feasibility of the proposed ADC architecture. The transistor-level simulation results show that 75.7dB SNDR is achieved in 5MHz bandwidth at 60MS/s. The power consumption is 748.9µW under 1.0V supply, which results in a FoM of 14.9fJ/conversion-step.
URL: https://globals.ieice.org/en_transactions/fundamentals/10.1587/transfun.E99.A.2473/_p

Copy

@ARTICLE{e99-a_12_2473,
author={Yu HOU, Zhijie CHEN, Masaya MIYAHARA, Akira MATSUZAWA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Design of Op-Amp Free SAR-VCO Hybrid ADC with 2nd-Order Noise Shaping in 65nm CMOS Technology},
year={2016},
volume={E99-A},
number={12},
pages={2473-2482},
abstract={This paper proposes a SAR-VCO hybrid 1-1 MASH ADC architecture, where a fully-passive 1^st-order noise-shaping SAR ADC is implemented in the first stage to eliminate Op-amp. A VCO-based ADC quantizes the residue of the SAR ADC with one additional order of noise shaping in the second stage. The inter-stage gain error can be suppressed by a foreground calibration technique. The proposed ADC architecture is expected to accomplish 2^nd-order noise shaping without Op-amp, which makes both high SNDR and low power possible. A prototype ADC is designed in a 65nm CMOS technology to verify the feasibility of the proposed ADC architecture. The transistor-level simulation results show that 75.7dB SNDR is achieved in 5MHz bandwidth at 60MS/s. The power consumption is 748.9µW under 1.0V supply, which results in a FoM of 14.9fJ/conversion-step.},
keywords={},
doi={10.1587/transfun.E99.A.2473},
ISSN={1745-1337},
month={December},}

Copy

TY - JOUR
TI - A Design of Op-Amp Free SAR-VCO Hybrid ADC with 2nd-Order Noise Shaping in 65nm CMOS Technology
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2473
EP - 2482
AU - Yu HOU
AU - Zhijie CHEN
AU - Masaya MIYAHARA
AU - Akira MATSUZAWA
PY - 2016
DO - 10.1587/transfun.E99.A.2473
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E99-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2016
AB - This paper proposes a SAR-VCO hybrid 1-1 MASH ADC architecture, where a fully-passive 1^st-order noise-shaping SAR ADC is implemented in the first stage to eliminate Op-amp. A VCO-based ADC quantizes the residue of the SAR ADC with one additional order of noise shaping in the second stage. The inter-stage gain error can be suppressed by a foreground calibration technique. The proposed ADC architecture is expected to accomplish 2^nd-order noise shaping without Op-amp, which makes both high SNDR and low power possible. A prototype ADC is designed in a 65nm CMOS technology to verify the feasibility of the proposed ADC architecture. The transistor-level simulation results show that 75.7dB SNDR is achieved in 5MHz bandwidth at 60MS/s. The power consumption is 748.9µW under 1.0V supply, which results in a FoM of 14.9fJ/conversion-step.
ER -