ASYL-SdF: A Synthesis Tool for Dependability in Controllers

Raphael ROCHET; Regis LEVEUGLE; Gabriele SAUCIER

ASYL-SdF: A Synthesis Tool for Dependability in Controllers

Raphael ROCHET, Regis LEVEUGLE, Gabriele SAUCIER

Full Text Views

0

Share
Cite this

Summary :

Synthesis tools are now extensively used in the VLSI circuit design process. They allow a much higher design productivity, but the designer often does not directly control the circuit structure. Thus, when circuits are dedicated to dependable applications, designers have difficulties in implementing manually the devices needed to obtain fault detection or tolerance capabilities. The ASYL-SdF System has been developed over the last few years in order to avoid this break in the design flow, and to facilitate the designer's work when dependability is targeted. This paper gives an overview of the resulting tool, its synthesis flow for fault detection and fault tolerance in Finite State Machines, its limitations and the current developments. Actual circuit implementation results are given in terms of area overheads, expected reliability and experimental fault detection coverage.

Publication: IEICE TRANSACTIONS on Information Vol.E79-D No.10 pp.1382-1388

Publication Date: 1996/10/25

Publicized

Online ISSN

DOI

Type of Manuscript: Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design)

Category: High-Level Synthesis

Cite this

Copy

Raphael ROCHET, Regis LEVEUGLE, Gabriele SAUCIER, "ASYL-SdF: A Synthesis Tool for Dependability in Controllers" in IEICE TRANSACTIONS on Information, vol. E79-D, no. 10, pp. 1382-1388, October 1996, doi: .
Abstract: Synthesis tools are now extensively used in the VLSI circuit design process. They allow a much higher design productivity, but the designer often does not directly control the circuit structure. Thus, when circuits are dedicated to dependable applications, designers have difficulties in implementing manually the devices needed to obtain fault detection or tolerance capabilities. The ASYL-SdF System has been developed over the last few years in order to avoid this break in the design flow, and to facilitate the designer's work when dependability is targeted. This paper gives an overview of the resulting tool, its synthesis flow for fault detection and fault tolerance in Finite State Machines, its limitations and the current developments. Actual circuit implementation results are given in terms of area overheads, expected reliability and experimental fault detection coverage.
URL: https://globals.ieice.org/en_transactions/information/10.1587/e79-d_10_1382/_p

Copy

@ARTICLE{e79-d_10_1382,
author={Raphael ROCHET, Regis LEVEUGLE, Gabriele SAUCIER, },
journal={IEICE TRANSACTIONS on Information},
title={ASYL-SdF: A Synthesis Tool for Dependability in Controllers},
year={1996},
volume={E79-D},
number={10},
pages={1382-1388},
abstract={Synthesis tools are now extensively used in the VLSI circuit design process. They allow a much higher design productivity, but the designer often does not directly control the circuit structure. Thus, when circuits are dedicated to dependable applications, designers have difficulties in implementing manually the devices needed to obtain fault detection or tolerance capabilities. The ASYL-SdF System has been developed over the last few years in order to avoid this break in the design flow, and to facilitate the designer's work when dependability is targeted. This paper gives an overview of the resulting tool, its synthesis flow for fault detection and fault tolerance in Finite State Machines, its limitations and the current developments. Actual circuit implementation results are given in terms of area overheads, expected reliability and experimental fault detection coverage.},
keywords={},
doi={},
ISSN={},
month={October},}

Copy

TY - JOUR
TI - ASYL-SdF: A Synthesis Tool for Dependability in Controllers
T2 - IEICE TRANSACTIONS on Information
SP - 1382
EP - 1388
AU - Raphael ROCHET
AU - Regis LEVEUGLE
AU - Gabriele SAUCIER
PY - 1996
DO -
JO - IEICE TRANSACTIONS on Information
SN -
VL - E79-D
IS - 10
JA - IEICE TRANSACTIONS on Information
Y1 - October 1996
AB - Synthesis tools are now extensively used in the VLSI circuit design process. They allow a much higher design productivity, but the designer often does not directly control the circuit structure. Thus, when circuits are dedicated to dependable applications, designers have difficulties in implementing manually the devices needed to obtain fault detection or tolerance capabilities. The ASYL-SdF System has been developed over the last few years in order to avoid this break in the design flow, and to facilitate the designer's work when dependability is targeted. This paper gives an overview of the resulting tool, its synthesis flow for fault detection and fault tolerance in Finite State Machines, its limitations and the current developments. Actual circuit implementation results are given in terms of area overheads, expected reliability and experimental fault detection coverage.
ER -