This paper proposes the minimum transition random X-filling (MTR-fill) technique, which is a new X-filling method, to reduce the amount of power dissipation during scan-based testing. In order to model the amount of power dissipated during scan load/unload cycles, the total weighted transition metric (TWTM) is introduced, which is calculated by the sum of the weighted transitions in a scan-load of a test pattern and a scan-unload of a test response. The proposed MTR-fill is implemented by simulated annealing method. During the annealing process, the TWTM of a pair of test patterns and test responses are minimized. Simultaneously, the MTR-fill attempts to increase the randomness of test patterns in order to reduce the number of test patterns needed to achieve adequate fault coverage. The effectiveness of the proposed technique is shown through experiments for ISCAS'89 benchmark circuits.

In this paper, we propose a new clustered reconfigurable interconnect network (CRIN) BIST that can improve the embedding probabilities of random-pattern-resistant-patterns. A simulated annealing based algorithm that maximizes the embedding probabilities of scan test cubes has been developed to reorder scan cells. Experimental results demonstrate that the proposed CRIN BIST technique reduces test time by 35% and the storage requirement by 39% in comparison with previous work.