An all-digital fully-synthesizable PVT-tolerant clock data recovery (CDR) architecture for wireline chip-to-chip interconnects is presented. The proposed architecture enables the co-synthesis of the CDR with the digital core. By eliminating the resource hungry manual layout and interfacing steps, which are necessary for conventional CDR topologies, the design process and the time-to-market can be drastically improved. Besides, the proposed CDR architecture enables the re-usability of majority of the sub-systems which enables easy migration to different process nodes. The proposed CDR is also equipped with a self-calibration scheme for ensuring tolerence over PVT. The proposed fully-syntehsizable CDR was implemented in 28nm FDSOI. The system achieves a maximum data rate of 10.06Gbps while consuming a power of 16.1mW from a 1V power supply.

Interconnect Length Distribution (ILD) represents the correlation between the number of interconnects and their length. The ILD can predict power consumption, clock frequency, chip size, etc. High core utilization and small circuit area have been reported to improve chip performance. We propose an ILD model to predict the correlation between core utilization and chip performance. The proposed model predicts the influences of interconnect length and interconnect density on circuit performances. As core utilization increases, small and simple circuits improve the performances. In large complex circuits, decreasing the wire coupling capacitance is more important than decreasing the total interconnect length for improvement of chip performance. The proposed ILD model expresses the actual ILD more accurately than conventional models.

There are enlarged requirements of millimeter-wave beamforming phased-array transceivers and high-order modulation multi-input multi-output (MIMO) transceivers. High-performance integrated RF switches are regarded as one of the most critical components for those transceivers to support signal channel distribution and path redundancy. This paper introduces a CMOS high-isolation and low-loss RF switch with a novel switched parallel LC resonance network. The proposed single-pole double-throw (SPDT) RF switch realizes 68dB port isolation and 1.0dB insertion loss with an active area of 0.034mm2. The SPDT RF switch is composed of two series-shunt transistor pairs with body-floating technology and a switched parallel LC network. The network uses a turned-off series transistor to resonate out off-capacitance Coff. The measured output third-order intercept (OIP3) is higher than 21dBm. The proposed SPDT RF switch maintains return losses of all working ports less than 10dB from 8GHz to 20GHz. The high-performance SPDT RF switch is fabricated in standard 65-nm CMOS technology.

This paper presents a 20 GHz push-push VCO realized by a 10 GHz super-harmonic coupled quadrature oscillator for a quadrature 60 GHz frequency synthesizer. The output nodes are peaked by a tunable second harmonic resonator. The proposed VCO is implemented in 65 nm CMOS process. It achieves a tuning range of 3.5 GHz from 16.1 GHz to 19.6 GHz with a phase noise of -106 dBc/Hz at 1 MHz offset. The power consumption of the core oscillators is 10.3 mW and an FoM of -181.3 dBc/Hz is achieved.

An L-2L through-line de-embedding method has been verified up to millimeter wave frequency. The parasitics of the pad can be modeled from the L-2L through-line. Measurement results of the transmission lines and transistors can be de-embedded by subtracting the parasitic matrix of the pad. Therefore, the de-embedding patterns, which is used for modeling active and passive devices, decrease greatly and the chip area also decreases. A one-stage amplifier is firstly implemented for helping verifying the de-embedding results. After that a four-stage 60 GHz amplifier has been fabricated in CMOS 65 nm process. Experimental results show that the four-stage amplifier realizes an input matching better than -10.5 dB and an output matching better than -13 dB at 61 GHz. A small signal power gain of 16.4 dB and a 1 dB output compression point of 4.6 dBm are obtained with a DC current consumption of 128 mA from a 1.2 V power supply. The chip size is 1.5 mm 0.85 mm.

This paper concerns a new model for estimating the wire length distribution (WLD) of a system-on-a-chip (SoC). The WLD represents the correlation between wire length and the number of interconnects, and we can predict circuit performances such as power consumption, maximum clock frequency, and chip size from the WLD. A WLD model considering core utilization has been proposed, and the core utilization has a large impact on circuit performance. However, the WLD model can treat only a one-function circuit. We propose a new WLD model considering core utilization to estimate the wire length distribution of SoC, which consists of several different-function macroblocks. We present an optimization method to determine each core utilization of macroblocks.