A low-power sub-1-V self-biased low-voltage reference is proposed for micropower electronic applications based on body effect. The proposed reference has a very low temperature dependence by using a MOSFET with body effect compared with other reported low-power references. An HSPICE simulation shows that the reference voltage and the total power dissipation are 181 mV and 1.1 µW, respectively. The temperature coefficient of the reference voltage is 33 ppm/ at temperatures from -40 to 100. The supply voltage can be as low as 0.95 V in a standard CMOS 0.35 µm technology with threshold voltages of about 0.5 V and -0.65 V for n-channel and p-channel MOSFETs, respectively. Furthermore, the supply voltage dependence is -0.36 mV/V (Vdd=0.95-3.3 V).

The traditional Markov prediction methods of the taxi destination rely only on the previous 2 to 3 GPS points. They negelect long-term dependencies within a taxi trajectory. We adopt a Recurrent Neural Network (RNN) to explore the long-term dependencies to predict the taxi destination as the multiple hidden layers of RNN can store these dependencies. However, the hidden layers of RNN are very sensitive to small perturbations to reduce the prediction accuracy when the amount of taxi trajectories is increasing. In order to improve the prediction accuracy of taxi destination and reduce the training time, we embed suprisal-driven zoneout (SDZ) to RNN, hence a taxi destination prediction method by regularized RNN with SDZ (TDPRS). SDZ can not only improve the robustness of TDPRS, but also reduce the training time by adopting partial update of parameters instead of a full update. Experiments with a Porto taxi trajectory data show that TDPRS improves the prediction accuracy by 12% compared to RNN prediction method in literature[4]. At the same time, the prediction time is reduced by 7%.

Inspired from the idea of data representation in manifold learning, we derive a novel model which combines the original training images and their tangent vectors to represent each image in the testing set. Different from the previous methods, the L1 norm is used to control the reconstruction error. Considering the fact that the objective function in the proposed model is non-smooth, we utilize the majorization minimization (MM) method to solve the proposed optimization model. It is interesting to note that at each iteration a quadratic optimization problem is formulated and its analytical solution can be achieved, thereby making the proposed algorithm effective. Extensive experiments on face images demonstrate that our method achieves better performance than some previous methods.

This paper presents a high jitter performance injection-locked clock multiplier (ILCM) using an ultra-low power (ULP) voltage-controlled oscillator (VCO) for IoT application in 65-nm CMOS. The proposed transformer-based VCO achieves low flicker noise corner and sub-100µW power consumption. Double cross-coupled NMOS transistors sharing the same current provide high transconductance. The network using high-Q factor transformer (TF) provides a large tank impedance to minimize the current requirement. Thanks to the low current bias with a small conduction angle in the ULP VCO design, the proposed TF-based VCO's flicker noise can be suppressed, and a good PN can be achieved in flicker region (1/f3) with sub-100µW power consumption. Thus, a high figure-of-merit (FoM) can be obtained at both 100kHz and 1MHz without additional inductor. The proposed VCO achieves phase noise of -94.5/-115.3dBc/Hz at 100kHz/1MHz frequency offset with a 97µW power consumption, which corresponds to a -193/-194dBc/Hz VCO FoM at 2.62GHz oscillation frequency. The measurement results show that the 1/f3 corner is below 60kHz over the tuning range from 2.57GHz to 3.40GHz. Thanks to the proposed low power VCO, the total ILCM achieves 78 fs RMS jitter while using a high reference clock. A 960 fs RMS jitter can be achieved with a 40MHz common reference and 107µW corresponding power.

Environment perception is an important task for intelligent vehicles applications. Typically, multiple sensors with different characteristics are employed to perceive the environment. To robustly perceive the environment, the information from the different sensors are often integrated or fused. In this article, we propose to perform the sensor fusion and registration of the LIDAR and stereo camera using the particle swarm optimization algorithm, without the aid of any external calibration objects. The proposed algorithm automatically calibrates the sensors and registers the LIDAR range image with the stereo depth image. The registered LIDAR range image functions as the disparity map for the stereo disparity estimation and results in an effective sensor fusion mechanism. Additionally, we perform the image denoising using the modified non-local means filter on the input image during the stereo disparity estimation to improve the robustness, especially at night time. To evaluate our proposed algorithm, the calibration and registration algorithm is compared with baseline algorithms on multiple datasets acquired with varying illuminations. Compared to the baseline algorithms, we show that our proposed algorithm demonstrates better accuracy. We also demonstrate that integrating the LIDAR range image within the stereo's disparity estimation results in an improved disparity map with significant reduction in the computational complexity.

This paper presents an ontology-based driving decision making system, which can promptly make safety decisions in real-world driving. Analyzing sensor data for improving autonomous driving safety has become one of the most promising issues in the autonomous vehicles research field. However, representing the sensor data in a machine understandable format for further knowledge processing still remains a challenging problem. In this paper, we introduce ontologies designed for autonomous vehicles and ontology-based knowledge base, which are used for representing knowledge of maps, driving paths, and perceived driving environments. Advanced Driver Assistance Systems (ADAS) are developed to improve safety of autonomous vehicles by accessing to the ontology-based knowledge base. The ontologies can be reused and extended for constructing knowledge base for autonomous vehicles as well as for implementing different types of ADAS such as decision making system.

The manner of a person's eye movement conveys much about nonverbal information and emotional intent beyond speech. This paper describes work on expressing emotion through eye behaviors in virtual agents based on the parameters selected from the AU-Coded facial expression database and real-time eye movement data (pupil size, blink rate and saccade). A rule-based approach to generate primary (joyful, sad, angry, afraid, disgusted and surprise) and intermediate emotions (emotions that can be represented as the mixture of two primary emotions) utilized the MPEG4 FAPs (facial animation parameters) is introduced. Meanwhile, based on our research, a scripting tool, named EEMML (Emotional Eye Movement Markup Language) that enables authors to describe and generate emotional eye movement of virtual agents, is proposed.

The peer-assisted streaming paradigm has been widely employed to distribute live video data on the internet recently. In general, the mesh-based pull approach is more robust and efficient than the tree-based push approach. However, pull protocol brings about longer streaming delay, which is caused by the handshaking process of advertising buffer map message, sending request message and scheduling of the data block. In this paper, we propose a new approach, mesh-push, to address this issue. Different from the traditional pull approach, mesh-push implements block scheduling algorithm at sender side, where the block transmission is initiated by the sender rather than by the receiver. We first formulate the optimal upload bandwidth utilization problem, then present the mesh-push approach, in which a token protocol is designed to avoid block redundancy; a min-cost flow model is employed to derive the optimal scheduling for the push peer; and a push peer selection algorithm is introduced to reduce control overhead. Finally, we evaluate mesh-push through simulation, the results of which show mesh-push outperforms the pull scheduling in streaming delay, and achieves comparable delivery ratio at the same time.

An energy management circuit is proposed for self-powered ubiquitous sensor modules using vibration-based energy. With the proposed circuit, the sensor modules work with low duty cycle operation. Moreover, a two-tank circuit as a part of the energy management circuit is utilized to solve the problem that the average power density of ambient energy always varies with time while the power consumption of the sensor modules is constant and larger than it. In addition, the long start-up time problem is also avoided with the timing control of the proposed energy management circuit. The CMOS implementation and silicon verification results of the proposed circuit are also presented. Its validity is further confirmed with a vibration-based energy generation. The sensor module is used to supervise the vibration of machines and transfer the vibration signal discontinuously. A piezoelectric element acts as the vibration-to-electricity converter to realize battery-free operation.

Regarding the enlarged array size for the 5G new radio (NR) millimeter-wave phased-array transceivers, an improved phase tuning resolution will be required to support the accurate beam control. This paper introduces a CMOS implementation of an active vector-summing phase shifter. The proposed phase shifter realizes a 6-bit phase shifting with an active area of 0.32mm2. To minimize the gain variation during the phase tuning, a gain error compensation technique is proposed. After the compensation, the measured gain variation within the 5G NR band n257 is less than 0.9dB. The corresponding RMS gain error is less than 0.2dB. The measured RMS phase error from 26.5GHz to 29.5GHz is less than 1.2°. Gain-invariant, high-resolution phase tuning is realized by this work. Considering the error vector magnitude (EVM) performance, the proposed phase shifter supports a maximum data rate of 11.2Gb/s in 256QAM with a power consumption of 25.2mW.

Many image-processing techniques are based on texture features or gradation features of the image. However, Landsat images are complex; they also include physical features of reflection radiation and heat radiation from land cover. In this paper, we describe a method of constructing a super-resolution image of Band 6 of the Landsat TM sensor, oriented to analysis of an agricultural area, by combining information (texture features, gradation features, physical features) from other bands. In this method, a knowledge-based hierarchical classifier is first used to identify land cover in each pixel and then the least-squares approach is applied to estimate the mean temperature of each type of land cover. By reassigning the mean temperature to each pixel, a finer spatial resolution is obtained in Band 6. Computational results show the efficiency of this method.

Existing trajectory prediction methods suffer from the “data sparsity” and neglect “time awareness”, which leads to low accuracy. Aiming to the problem, we propose a fast time-aware sparse trajectories prediction with tensor factorization method (TSTP-TF). Firstly, we do trajectory synthesis based on trajectory entropy and put synthesized trajectories into the original trajectory space. It resolves the sparse problem of trajectory data and makes the new trajectory space more reliable. Then, we introduce multidimensional tensor modeling into Markov model to add the time dimension. Tensor factorization is adopted to infer the missing regions transition probabilities to further solve the problem of data sparsity. Due to the scale of the tensor, we design a divide and conquer tensor factorization model to reduce memory consumption and speed up decomposition. Experiments with real dataset show that TSTP-TF improves prediction accuracy generally by as much as 9% and 2% compared to the Baseline algorithm and ESTP-MF algorithm, respectively.

This paper concerned the research on a memristive chaotic system and the generated random sequence; by constructing a piecewise-linear memristor model, a kind of chaotic system is constructed, and corresponding numerical simulation and dynamical analysis are carried out to show the dynamics of the new memristive chaotic system. Finally the proposed memristive chaotic system is used to generate random sequence for the possible application in encryption field.

This paper presents a high-resolution and low-insertion-loss CMOS hybrid phase shifter with a nonuniform matching technique for satellite communication (SATCOM). The proposed hybrid phase shifter includes three 45° coarse phase-shifting stages and one 45° fine phase-tuning stage. The coarse stages are realized by bridged-T switch-type phase shifters (STPS) with 45° phase steps. The fine-tuning stage is based on a reflective-type phase shifter (RTPS) with two identical LC load tanks for phase tuning. A 0.8° phase resolution is realized by this work to support fine beam steering for the SATCOM. To further reduce the chain insertion loss, a nonuniform matching technique is utilized at the coarse stages. For the coarse and fine stages, the measured RMS gain errors at 29GHz are 0.7dB and 0.3dB, respectively. The measured RMS phase errors are 0.8° and 0.4°, respectively. The proposed hybrid phase shifter maintains return losses of all phase states less than -12dB from 24GHz to 34GHz. The presented hybrid phase shifter is fabricated in a standard 65-nm CMOS technology with a 0.14mm2 active area.

The RC mismatch among S/H stages for time-interleaved ADCs causes a phase error and a gain error and the phase error is dominant. The paper points out that clock skew and the phase error caused by the RC mismatch have similar effects on the sampling error and then can be compensated with the clock skew compensation. Simulation results agree well with the theoretical analysis. With the phase error compensation of RC mismatch, the SNDR in 14b ADC can be improved by more than 15 dB in the case that the bandwidth of S/H circuits is 3 times the sampling frequency. This paper also proposes a method of clock skew and RC mismatch compensation in time-interleaved sample-and-hold (S/H) circuits by sampling clock phase adjusting.

This paper gives a detailed presentation of a "vision chip" for a very fast detection of motion vectors. The chip's design consists of a parallel pixel array and column parallel block-matching processors. Each pixel of the pixel array contains a photo detector, an edge detector and 4 bits of memory. In the detection of motion vectors, first, the gray level image is binarized by the edge detector and subsequently the binary edge data is used in the block matching processor. The block-matching takes place locally in pixel and globally in column. The chip can create a dense field of motion where a vector is assigned to each pixel by overlapping 2 2 target blocks. A prototype with 16 16 pixels and four block-matching processors has been designed and implemented. Preliminary results obtained by the prototype are shown.

This paper presents a miniaturized transformer-based ultra-low-power (ULP) LC-VCO with embedded supply pushing reduction techniques for IoT applications in 65-nm CMOS process. To reduce the on-chip area, a compact transformer patterned ground shield (PGS) is implemented. The transistors with switchable capacitor banks and associated components are placed underneath the transformer, which further shrinking the on-chip area. To lower the power consumption of VCO, a gm-stacked LC-VCO using the transformer embedded with PGS is proposed. The transformer is designed to provide large inductance to obtain a robust start-up within limited power consumption. Avoiding implementing an off/on-chip Low-dropout regulator (LDO) which requires additional voltage headroom, a low-power supply pushing reduction feedback loop is integrated to mitigate the current variation and thus the oscillation amplitude and frequency can be stabilized. The proposed ULP TF-based LC-VCO achieves phase noise of -114.8dBc/Hz at 1MHz frequency offset and 16kHz flicker corner with a 103µW power consumption at 2.6GHz oscillation frequency, which corresponds to a -193dBc/Hz VCO figure-of-merit (FoM) and only occupies 0.12mm2 on-chip area. The supply pushing is reduced to 2MHz/V resulting in a -50dBc spur, while 5MHz sinusoidal ripples with 50mVPP are added on the DC supply.

This paper introduces a high-resolution and compact CMOS switch-type phase shifter (STPS) for the 5th generation mobile network (5G) n260 band. In this work, totally four coarse phase shifting stages and a high-resolution tuning stage are included. The coarse stages based on the bridged-T topology is capable of providing 202.5° phase coverage with a 22.5° tuning step. To further improve the phase shifting resolution, a compact fine-tuning stage covering 23° is also integrated with the coarse stages. Sub-degree phase shifting resolution is realized for supporting the fine beam-steering and high-accuracy phase calibration in the 5G new radio. Simplified phase control algorithm and suppressed insertion loss can also be maintained by the proposed fine-tuning stage. In the measurement, the achieved RMS gain errors at 39 GHz are 0.1 dB and 0.4 dB for the coarse stages and fine stage, respectively. The achieved RMS phase errors at 39 GHz are 3.1° for the coarse stages and 0.1° for the fine stage. Within 37 GHz to 40 GHz, the measured return loss within all phase-tuning states is always better than -14 dB. The proposed phase shifter consumes a core area of only 0.12mm2 with 65-nm CMOS process, which is area-efficient.

There are enlarged requirements of millimeter-wave beamforming phased-array transceivers and high-order modulation multi-input multi-output (MIMO) transceivers. High-performance integrated RF switches are regarded as one of the most critical components for those transceivers to support signal channel distribution and path redundancy. This paper introduces a CMOS high-isolation and low-loss RF switch with a novel switched parallel LC resonance network. The proposed single-pole double-throw (SPDT) RF switch realizes 68dB port isolation and 1.0dB insertion loss with an active area of 0.034mm2. The SPDT RF switch is composed of two series-shunt transistor pairs with body-floating technology and a switched parallel LC network. The network uses a turned-off series transistor to resonate out off-capacitance Coff. The measured output third-order intercept (OIP3) is higher than 21dBm. The proposed SPDT RF switch maintains return losses of all working ports less than 10dB from 8GHz to 20GHz. The high-performance SPDT RF switch is fabricated in standard 65-nm CMOS technology.