GaAs 10 Gb/s 64:1 Multiplexer/Demultiplexer chip sets have been successfully developed. The 64-bit 156 Mb/s parallel data output or input of these chip sets can be directly connected to CMOS LSIs. These chip sets consist of a 10Gb/s 4: 1 MUX IC, a 10 Gb/s 1: 4 DEMUX IC, four 2.5 Gb/s 16: 1 MUX LSIs and four 2.5 Gb/s 1: 16 DEMUX LSIs. This multi-chip construction is adopted for low power dissipation and high yield. The basic circuit employed in the 10 Gb/s4: 1 MUX/DEMUX ICs is an SCFL circuit using 0.4 µm-gate FETs with a power supply of -5.2 V, and that in 2.5 Gb/s 16: 1 MUX/DEMUX LSIs is a DCFL circuit using 0.6 µm-gate FETs with a power supply of -2.0 V. These chip sets have functions for synchronization among these ICs and to enable bit shift to make the system design easier. In the 10 Gb/s 4: 1 MUX IC, a timing adjuster is adopted. This timing adjuster can delay the timing of the most critical path by 50 ps. Even if the delay times are out of order due to fluctuations in process, temperature, power supply voltage and other factors, this timing can be revised and the 4: 1 MUX IC can operate at 10 Gb/s. Furthermore, a 48-pin quad flat package for 10 Gb/s 4: 1 MUX/DEMUX ICs has been newly developed. The measured insertion loss is 1.7 dB (at 10 GHz), and the isolation is less than -20 dB (at 10 GHz). These values are sufficient in practical usage. Measurements of these chip sets show desirable performance at the target 10 Gb/s. The power dissipations of the 64: 1 MUX/DEMUX chip sets are 10.3 W and 8.2 W, respectively. These chip sets is expected to contribute to high speed telecommunication systems.

A 0.15 µm T-shaped gate AlInAs/InGaAs high electron mobility transistor (HEMT) with an excellent RF performance has been developed using selective wet gate recess etching. The gate recess is formed by a pH-adjusted citric acid/NH4OH/H2O2 mixture with an etching selectivity of more than 30 for InGaAs over AlInAs. The standard deviation of saturation drain current (Idss) is as small as 3.2 mA for an average Idss of 47 mA on a 3 inch diameter InP wafer. The etching time for recess formation is optimized and an ft of 130 GHz and an MSG of 10 dB at 60 GHz are obtained. The extremely low minimum noise figure (Fmin) of 0.9 dB with an associated gain (Ga) of 7.0 dB has been achieved at 60 GHz for a SiON-passivated device. This noise performance is comparable to the lowest value of Fmin ever reported for an AlInAs/InGaAs HEMT with a passivation film.

A Q-band high gain and low noise Variable Gain Amplifier (VGA) module using dual gate AlGaAs/InGaAs pseudomorphic HEMTs has been developed. The dual gate HEMT can be fabricated by the same process of the single gate HEMT which has the gate length of 0.15 µm. The Q-band VGA module consists of a 1-stage low noise amplifier (LNA) MMIC using a single gate HEMT and a 2-stage VGA MMIC using dual gate HEMTs. During the design, an accurate noise modeling is introduced to achieve low noise performance. A fully passivated film is employed to achieve reliability. The VGA module has a gain of more than 20 dB from 41 GHz to 52 GHz and a maximum gain of 24.5 dB at 50 GHz. A gain control range of more than 30 dB is achieved in the same frequency range. A phase deviation is less than 10 degrees in 10 dB gain control range. A minimum noise figure of 1.8 dB with an associated gain of 22 dB is achieved at 43 GHz and the noise figure is less than 2.5 dB with associated gain of more than 20 dB from 41 GHz to 46 GHz when biased for low noise figure. This performance is comparable with the best data ever reported for LNAs at Q-band including both GaAs based HEMTs and InP based HEMTs.