We present a high performance AlGaAs/GaAs power HBT with very low thermal resistance for digital cellular phones. Device structure with emitter air-bridge is utilized and device layout is optimized to reduce thermal resistance based on three-dimensional thermal flow analysis, and in spite of a rather thick substrate (100 µm), which achieved a low thermal resistance of 23/W for a multi-finger (440 µm240 fingers) HBT. This 40 finger HBT achieved power added efficiency (PAE) of over 53%, 29.1 dBm output power (Pout) and high associated gain (Ga) of 13.5 dB with 50 kHz adjacent channel leakage power (Padj) of less than -48 dBc under a 948 MHz π/4-shifted QPSK modulation with 3.4 V emitter-collector voltage. We also investigated the difference of RF performance between two bias modes (constant base voltage and current), and found which mode is adequate for each stage in several stage power amplifier for the first time.

GaAs 10 Gb/s 64:1 Multiplexer/Demultiplexer chip sets have been successfully developed. The 64-bit 156 Mb/s parallel data output or input of these chip sets can be directly connected to CMOS LSIs. These chip sets consist of a 10Gb/s 4: 1 MUX IC, a 10 Gb/s 1: 4 DEMUX IC, four 2.5 Gb/s 16: 1 MUX LSIs and four 2.5 Gb/s 1: 16 DEMUX LSIs. This multi-chip construction is adopted for low power dissipation and high yield. The basic circuit employed in the 10 Gb/s4: 1 MUX/DEMUX ICs is an SCFL circuit using 0.4 µm-gate FETs with a power supply of -5.2 V, and that in 2.5 Gb/s 16: 1 MUX/DEMUX LSIs is a DCFL circuit using 0.6 µm-gate FETs with a power supply of -2.0 V. These chip sets have functions for synchronization among these ICs and to enable bit shift to make the system design easier. In the 10 Gb/s 4: 1 MUX IC, a timing adjuster is adopted. This timing adjuster can delay the timing of the most critical path by 50 ps. Even if the delay times are out of order due to fluctuations in process, temperature, power supply voltage and other factors, this timing can be revised and the 4: 1 MUX IC can operate at 10 Gb/s. Furthermore, a 48-pin quad flat package for 10 Gb/s 4: 1 MUX/DEMUX ICs has been newly developed. The measured insertion loss is 1.7 dB (at 10 GHz), and the isolation is less than -20 dB (at 10 GHz). These values are sufficient in practical usage. Measurements of these chip sets show desirable performance at the target 10 Gb/s. The power dissipations of the 64: 1 MUX/DEMUX chip sets are 10.3 W and 8.2 W, respectively. These chip sets is expected to contribute to high speed telecommunication systems.

A 100 W, low distortion AlGaAs/GaAs heterostructure FET has been developed for CDMA cellular base stations. This FET employs the longest gate finger ever reported of 800 µm to shrink the chip size. The size of the chip and the package are miniaturized to 1.242.6 mm2 and 17.4 24.0 mm2, respectively. The developed FET exhibits 100 W (50 dBm) saturation output power, and 11.5 dB power gain at 1 dB gain compression at 2.1 GHz. The third-order intermodulation distortion and the power-added efficiency under the two-tone test condition (Δf=1 MHz) are -35 dBc and 24%, respectively at 42 dBm output power, that is 8 dB back off from the saturation power.

In order to establish design and measurement technologies for an LSI that features high speed operation and low power dissipation, GaAs 2.5 Gbps 16 bit MUX/DEMUX LSIs have been successfully developed. DCFL is employed as a basic gate in order to reduce the power dissipation. For the purpose of achieving stable operation against the transistor parameter deviation, a timing design called clock tracking is employed. Moreover, to ensure accurate performance measurement, a new measurement system is introduced. The measurement system consists of an error rate detector (ERD), a pulse pattern generator (PPG) and a high speed tester (HST). The performances tested by the measurement system show the power consumptions of MUX and DEMUX LSIs are 1.35 W and 0.95 W. Input phase margin of DEMUX LSI is 290 degrees at 2.5 Gbps operation. The technologies obtained through development of these MUX/DEMUX LSIs are applicable to other high speed and low power LSIs.

A new harmonic termination that controls the waveform of the drain current to be rectangular is developed for high-efficiency power amplifier modules. Its harmonic termination is a short circuit at the third harmonic and a non-short circuit at the second harmonic. It is found experimentally and confirmed by simulation that the load-matching condition at the third-order harmonic improves the efficiency of a transistor by more than 13%. By using this tuning, 57.7% power-added efficiency of the module is achieved at the output power of 29.9 dBm with ACP of -50 dBc, NACP of -65 dBc at 925 MHz and Vdd of 3.5 V.

A Q-band high gain and low noise Variable Gain Amplifier (VGA) module using dual gate AlGaAs/InGaAs pseudomorphic HEMTs has been developed. The dual gate HEMT can be fabricated by the same process of the single gate HEMT which has the gate length of 0.15 µm. The Q-band VGA module consists of a 1-stage low noise amplifier (LNA) MMIC using a single gate HEMT and a 2-stage VGA MMIC using dual gate HEMTs. During the design, an accurate noise modeling is introduced to achieve low noise performance. A fully passivated film is employed to achieve reliability. The VGA module has a gain of more than 20 dB from 41 GHz to 52 GHz and a maximum gain of 24.5 dB at 50 GHz. A gain control range of more than 30 dB is achieved in the same frequency range. A phase deviation is less than 10 degrees in 10 dB gain control range. A minimum noise figure of 1.8 dB with an associated gain of 22 dB is achieved at 43 GHz and the noise figure is less than 2.5 dB with associated gain of more than 20 dB from 41 GHz to 46 GHz when biased for low noise figure. This performance is comparable with the best data ever reported for LNAs at Q-band including both GaAs based HEMTs and InP based HEMTs.

A refection type and loaded-line type phase shifter switching multi phase-states has been described. This novel phase shifter circuit is constructed by adding switching FETs to a conventional 2-phase-state phase shifter. A conventional 3 bit phase shifter can be replaced by this type of phase shifter. The total chip size is reduced to 2/3. This paper reports on the design, fabrication, and performance of the novel reflection-type and loaded-line-type phase shifter MMICs.

An ultra low noise 50-GHz-Band amplifier (LNA) MMIC has been developed using an AlGaAs/InGaAs pseudomorphic HEMT. A noise figure of 1.8 dB with an associated gain of 8.1 dB is achieved at 50 GHz. The noise figure is less than 2.0 dB from 50 GHz to 52.5 GHz. This is the state-of-the-art noise figure for low noise amplifiers around 50 GHz. The success of this LNA development came from the excellent HEMT and MMIC technologies and the accurate modeling of active and passive elements. Good agreement between measured and simulated data over the band from 40 GHz to 60 GHz is obtained.