This paper presents a triple-band WCDMA direct conversion receiver (DCR) IC that needs a small number of off-chip components and control signals from digital baseband (DBB) IC. The DCR IC consists of 3 quadrature demodulators (QDEMs) with on-chip impedance matching circuit and an analog baseband block (ABB) that contains a low-pass filter (LPF) with fc automatic tuning circuit using no off-chip components and a linear-in-dB variable-gain amplifier (VGA) with on-chip analog high-pass filter (HPF). In order to make use of DBB control-free DC offset canceler, the DCR is designed to avoid large gain change under large interference that causes long transient response. In order to realize that characteristic without increasing quiescent current, the QDEM is used that employs class AB input stage and low-noise common mode feedback (CMFB) output stage. The DCR IC was fabricated in a SiGe BiCMOS process and occupies about 2.9 mm3.0 mm. The DCR needs SAW filters only for off-chip components and a gain control signal from DBB IC for AGC loop. The IIP3 of over -4.4 dBm for small signal input level and that of over +1.9 dBm for large signal input level are achieved. The gain compression of the desired signal is less than 0.3 dB for ACS Case-II condition.

A fast fc automatic tuning circuit suitable for WCDMA systems is proposed. The circuit employs master-slave architecture using digitally controlled Gm-C filter for avoiding long transient response. The tuning feedback loop contains a 2-bit up-down counter ADC for fast tuning operation. Furthermore, to avoid degradation of fc tuning accuracy due to reference feedthrough, an analog loop filter with notch located near reference frequency is used. The fast fc automatic tuning circuit is fabricated in a SiGe BiCMOS process. The tuning time within 200 µs is achieved for 35 chips from 2 lots and the standard deviation of 25.5 kHz is obtained for the average fc of 2.12 MHz.

This paper presents a single-chip RF tuner/OFDM demodulator for a mobile digital TV application called “1-segment broadcasting.” To achieve required performances for the single-chip receiver, a tunable technique for a low-noise amplifier (LNA) and spurious suppression techniques are proposed in this paper. Firstly, to receive all channels from 470 MHz to 770 MHz and to relax distortion characteristics of following circuit blocks such as an RF variable-gain amplifier and a mixer, a tunable technique for the LNA is proposed. Then, to improve the sensitivity, spurious signal suppression techniques are also proposed. The single-chip receiver using the proposed techniques is fabricated in 90 nm CMOS technology and total die size is 3.26 mm 3.26 mm. Using the tunable LNA and suppressing undesired spurious signals, the sensitivities of less than -98.6 dBm are achieved for all the channels.

A four-stage power amplifier (PA) with 10 GHz 1-dB bandwidth (56–66 GHz) is presented. The broadband performance is achieved owing to π-section interstage matching network. Three-stage-current-reuse topology is proposed to enhance efficiency. The amplifier has been fabricated in 65 nm digital CMOS. 18 dB power gain and 9.6 dBm saturated power (Psat) are achieved at 60 GHz. The PA consumes current of 50 mA at 1.2 V supply voltage, and has a peak power-added efficiency (PAE) of 13.6%. To the best of the authors' knowledge, this work shows the highest PAE among the reported CMOS PAs that covers the worldwide 9 GHz ISM millimeter-wave band with less-than-1.2 V supply voltage.

This paper presents a 1024-QAM OFDM signal capable WLAN receiver in 65nm CMOS technology. Thermal noise-based IQ frequency-independent mismatch correction and IQ frequency-dependent mismatch correction with baseband loopback are proposed for the self-calibration in the receiver. The measured image rejection ratio of the self-calibration is -56.3dB. The receiver achieves the extremely low EVM of -37.1dB even with wide channel bandwidth of 80MHz and has the ability to receive the 1024-QAM signal. The result indicates that the receiver is extendable for the 802.11ax compliant receiver that supports a higher density modulation scheme of MIMO.

This paper presents an analog front-end circuit for a 60-GHz proximity wireless communication receiver. The feature of the proposed analog front-end circuit is a bandwidth more than 1-GHz wide. To expand the bandwidth of a low-pass filter and a voltage gain amplifier, a technique to reduce the parasitic capacitance of a transconductance amplifier is proposed. Since the bandwidth is also limited by on-resistance of the ADC sampling switch, a switch separation technique for reduction of the on-resistance is also proposed. In a high-speed ADC, the SNDR is limited by the sampling jitter. The developed high resolution VCO auto tuning effectively reduces the jitter of PLL. The prototype is fabricated in 65nm CMOS. The analog front-end circuit achieves over 1-GHz bandwidth and 27.2-dB SNDR with 224mW Power consumption.