Ultrashallow p-type layers have been formed using an one-wafer type reactor for rapid vapor-phase doping (RVD) with lamp annealing system. Bipolar and MOS transistors were fabricated using the system for the first time. The process includes the injection of the B2H6 diffusion source gas with hydrogen carrier gas at room temperature and rapid thermal annealing using lamps. Ultrashallow boron doping was achieved at 900 for 60 seconds; that is, the junction depths were less the 60 nm with a peak boron concentration of between 1019 and 1020 cm-3. The sheet boron concentrations is controlled by adjusting the flow rate of B2H6. To show the potential of the process, bipolar and MOS transistors were fabricated. The base regions of conventional bipolar transistors were formed by rapid vapor-phase doping. Transistors with 20-nm base and emitter were fabricated and they showed current gain of 150. Shallow source and drain of PMOS transistors were also formed. The threshold voltage roll-off was suppressed down to gate length of 0.22 µm, while devices with BF2-implanted source and drain showed the roll-off below 0.5 µm. Devices with RVD-source and drain thus have drain current 1.5 times higher than those with BF2 ion implantation. RVD provides both good short-channel characteristics and high current drivability.

The degradation of I-V characteristics under constant emitter-base reverse voltage stress in advanced self-aligned bipolar transistors was analyzed. Experimental analyses have been taken the stress field effect into account when predicting hot-carrier degradation. These analyses showed that base current starts to increase when the reverse voltage stress is about 3 V. The dependence of the base current change on reverse voltages of more than 3 V was also investigated experimentally, and equations expressing hot-carrier degradation in terms of the exponential dependence of excess base current on both reverse stress voltage and stress-enhancing voltage related to emitter-base breakdown voltage were derived.

Single-drain PMOSFET's with a very shallow source and drain were fabricated using a new doping method called rapid vapor-phase doping (RVD). This process is carried out in hydrogen atmosphere using B2H6 as a source gas. By varying flow rate of B2H6 and the doping time, shallow boron doped layers which are suitable for source and drain regions of MOSFET's are formed. The fabricated RVD-PMOSFET's have 50-nm source and drain regions with peak concentration of 41020 cm-3 which were formed under the condition of 800, B2H6 flow rate of 50 ml/min. The junction depth was one third of those formed by conventional low-energy BF2 ion implantation. RVD-PMOSFET's showed normal operation down to poly-Si gate length Lg of 0.18 µm. The advantage of shallow junction was clearly shown by the threshold voltage roll-off characteristics, that is, it was suppressed down to 0.18 µm, whereas in conventional device, roll-off occurred below 0.6 µm. This better short channel behavior suggests that RVD forms shallow source and drain regions with weaker lateral diffusion. This result confirms that RVD is an effective method for forming shallow junctions for MOSFET's.

This paper describes a new soft-error-immune SICOS upward transistor memory cell suitable for ultra-high-speed bipolar RAMs. A cell size of 180 µm2, significantly smaller than the 500 µm2 in the conventional upward transistor cell, is achieved by marging an upward transistor and a Shottky barrier diode. A new very thin polysilicon resistor and 0.5-µm U-groove isolated SICOS technology are used to furher reduce cell size. The memory cell is about 105 times as immune to soft errors as downward transistor cells. A simulation shows that a 256-Kbit RAM with a write cycle time below 3 ns can be made using this memory cell.

A high-speed high-density self-aligned pnp technology for complementary bipolar ULSIs has been developed to achieve high-speed and low-power performance simultaneously. It is fully compatible with the npn process. A low sheet-resistance p+ buried layer and a low sheet-resistance extrinsic n+ polysilicon layer with U-grooved isolation enable the transistor size to be scaled down to about 20 µm2. Current gain of 85 with 4-V collector-emitter breakdown voltage was obtained without any leakage current arising from emitter-base forward tunneling or recombination, which indicates no extrinsic base encroachment problem. A shallow emitter junction depth of 45 nm and narrow base width of 30 nm, obtained by utilizing an optimized retrograded p-well, an arsenic-implanted intrinsic base, and emitter diffusion from BF2-implanted polysilicon, improve the maximum cutoff frequency to 35 GHz. The power dissipation of the pnp pull-down complementary emitter-follower ECL circuit with load capacitances is calculated to be reduced to 20-40% of a conventional ECL circuit.

Recent high-speed bipolar technologies based on SICOS (Sidewall Base Contact Structure) transistors are reviewed. Bipolar device structures that include polysilicon are key technologies for improving circuit characteristics. As the characteristics of the upward operated SICOS transistors are close to those of downward transistors, they can easily be applied in memory cells which have near-perfect soft-error-immunity. Newly developed process technologies for making shallow base and emitter junctions to improve circuit performance are also reviewed. Finally, complementary bipolar technology for low-power and high-speed circuits using pnp transistors, and a quasi-drift base transistor structure suitable for below 0.1 µm emitters are discussed.