RF under sampling is more suitable for Satellite receiver systems in comparison to terrestrial systems. In conventional RF under sampling the minimum sampling frequency (fs) should be atleast twice the system bandwidth; therefore for a system with a wide bandwidth, a relatively high fs is necessary. In this paper we propose a direct RF under sampling reception method that halves fs. The proposed f's is achieved by folding in band noise in half. A method of adapting f's for the reception of signals in different channels is also proposed; this ensures that the SNR is not degraded for any channel. To evaluate the proposed technique's performance and compare it to the conventional case a 3 channel, 1 GHz band test receiver and it's key device (i.e. S/H circuit) are developed. Using SNR and EVM as performance indexes, the performance of the proposed technique has been evaluated and compared to that of the conventional technique. The evaluation results show that the proposed technique can achieve the same performance as conventional RF under sampling for all 3 channels, using only half of the sampling frequency of the conventional technique.

In this paper, we propose a novel baseband (BB) phase shifter (PS) using a fixed-gain-amplifier (FGA) matrix. The proposed BB PS consists of 5 stages of a vector synthesis type FGA matrix with in-phase/quadrature-phase (I/Q) input/output interfaces. In order to achieve low gain variation between phase shift states, 3rd to 5th stages are designed to have a phase shift of +φi and -φi (i=3,4,5). To change between +φi and -φi phase shift states, two FGAs with DC bias in-phase/out-phase switches are used. The two FGAs have the same gain, therefore ideally no gain variation can be achieved. Using this configuration, phase shift error and gain variation caused by process mismatch and temperature variation can be reduced. Fabricated 5-bit BB PS has 3-dB bandwidth of 1.05GHz, root-mean-square (rms) phase errors lower than 2.2°, rms gain variations lower than 0.42dB. Power consumption of the PS core and output buffer are 4.9mW and 14.3mW, respectively. 1-dB compression output power is -12.5dBm. The fabricated PS shows that the total phase shift error and gain variation are within the required accuracy of a 5-bit PS with no requirement of calibration.

A fully-integrated system-on-chip (SoC) for Bluetooth Low Energy (BLE) with 3.2mA RX and 3.5mA TX current consumption is presented. To achieve both low current consumption and high performance, the SoC employs a sliding-IF architecture with high tolerance against out-of-band-blocking signals, a power management unit with improved efficiency, and techniques to reduce current in core circuits. The SoC achieves RX sensitivity of -93dBm and maximum output power of 0dBm. The SoC is in compliance with version 4.2 of the Bluetooth specifications and with the radio regulations of the FCC, ETSI, and ARIB. The SoC achieves the minimum level of current consumption for both RX and TX modes in the published product-level SoCs.

In this paper, a fully integrated 5 GHz voltage controlled oscillator (VCO) is presented. The VCO is designed with 0.18 µm silicon complementary metal oxide semiconductor (Si-CMOS) process. To achieve low phase noise, a novel varactors pair circuit is proposed to cancel effects of capacitance fluctuation that makes harmonic currents which increase phase noise of VCO. The VCO with the proposed varactor circuit has tuning range from 5.1 GHz to 6.1 GHz (relative value of 17.9%) and phase noise of lower than -110.8 dBc/Hz at 1 MHz offset over the full tuning range. Figure-of-merit-with-tuning-range (FOMT) of the proposed VCO is -182 dBc/Hz.