High efficiency video coding (HEVC) is a video compression standard that outperforms the predecessor H.264/AVC by doubling the compression efficiency. To enhance the intra prediction accuracy, 35 intra prediction modes were used in the prediction units (PUs), with partition sizes ranging from 4 × 4 to 64 × 64 in HEVC. However, the manifold prediction modes dramatically increase the encoding complexity. This paper proposes a fast mode- and depth-decision algorithm based on edge detection and reconfiguration to alleviate the large computational complexity in intra prediction with trivial degradation in accuracy. For mode decision, we propose pixel gradient statistics (PGS) and mode refinement (MR). PGS uses pixel gradient information to assist in selecting the prediction mode after rough mode decision (RMD). MR uses the neighboring mode information to select the best PU mode (BPM). For depth decision, we propose a partition reconfiguration algorithm to replace the original partitioning order with a more reasonable structure, by using the smoothness of the coding unit as a criterion in deciding the prediction depth. Smoothness detection is based on the PGS result. Experiment results show that the proposed method saves about 41.50% of the original processing time with little degradation (BD bitrate increased by 0.66% and BDPSNR decreased by 0.060dB) in the coding gain.

High efficiency video coding (HEVC) is a video compression standard that outperforms the predecessor H.264/AVC by doubling the compression efficiency. To enhance the coding accuracy, HEVC adopts sample adaptive offset (SAO), which reduces the distortion of reconstructed pixels using classification based non-linear filtering. In the traditional coding tree unit (CTU) grain based VLSI encoder implementation, during the pixel classification stage, SAO cannot use the raw samples in the boundary of the current CTU because these pixels have not been processed by deblocking filter (DF). This paper proposes a hardware-oriented category determination algorithm based on estimating the deblocking strengths on CTU boundaries and selectively adopting the promising samples in these areas during SAO classification. Compared with HEVC test mode (HM11.0), experimental results indicate that the proposed method achieves an average 0.13%, 0.14%, and 0.12% BD-bitrate reduction (equivalent to 0.0055dB, 0.0058dB, and 0.0097dB increases in PSNR) in CTU sizes of 64 × 64, 32 × 32, and 16 × 16, respectively.

This paper mainly discusses the time-difference-of-arrival (TDOA) estimation problem of digital modulation signal under impulsive noise and cochannel interference environment. Since the conventional TDOA estimation algorithms based on the second-order cyclic statistics degenerate severely in impulsive noise and the TDOA estimation algorithms based on correntropy are out of work in cochannel interference, a novel signal-selective algorithm based on the generalized cyclic correntropy is proposed, which can suppress both impulsive noise and cochannel interference. Theoretical derivation and simulation results demonstrate the effectiveness and robustness of the proposed algorithm.

The traditional multicast switch fabrics, which were mainly developed from the unicast switch fabrics, currently are not able to achieve high efficiency and flexible large-scale scalability. In the light of lattice theory and multicast concentrator, a novel multistage interconnection multicast switch fabric is proposed in this paper. Comparing to traditional multicast switch fabrics, this multicast switch fabric has the advantages of superior scalability, wire-speed, jitter-free multicast with low delay, and no queuing buffer. This paper thoroughly analyzes the performance of the proposed multicast switch fabric with supporting priority-based multicast. Simulations on packet loss rate and delay are discussed and presented at normalized load. Moreover, a detailed FPGA implementation is given. Practical network traffic tests provide evidence supporting the feasibility and stability of the proposed fabric.

Recent studies on switching fabrics mainly focus on the switching schedule algorithms, which aim at improving the throughput (a key performance metric). However, the delay (another key performance metric) of switching fabrics cannot be well guaranteed. A good switching fabric should be endowed with the properties of high throughput, delay guarantee, low component complexity and high-speed multicast, which are difficult for conventional switching fabrics to achieve. This has fueled great interest in designing a new switching fabric that can support large-scale extension and high-speed multicast. Motivated by this, we reuse the self-routing Boolean concentrator network and embed a model of multicast packet copy separation in front to construct a load-balanced multicast switching fabric (LB-MSF) with delay guarantee. The first phase of LB-MSF is responsible for balancing the incoming traffic into uniform cells while the second phase is in charge of self-routing the cells to their final destinations. In order to improve the throughput, LB-MSF is combined with the merits of erasure codes against packet loss. Experiments and analyses verify that the proposed fabric is able to achieve high-speed multicast switching and suitable for building super large-scale switching fabric in Next Generation Network(NGN) with all the advantages mentioned above. Furthermore, a prototype of the proposed switch is developed on FPGA, and presents excellent performance.

This paper presents an overview of the advance of the China millimeter-wave multiple gigabit (CMMG) wireless local area network (WLAN) system which operates in the 45 GHz frequency band. The CMMG WLAN system adopts the multiple antennas technologies to support data rate up to 15Gbps. During the progress of CMMG WLAN standardization, some new key technologies were introduced to adapt the millimeter-wave characteristic, including the usage of the zero correlation zone (ZCZ) sequence, a novel lower density parity check code (LDPC)-based packet encoding, and multiple input multiple output (MIMO) single carrier transmission. Extensive numerical results and system prototype test are also given to validate the performance of the technologies adopted by CMMG WLAN system.

Comparing with search pattern motion estimation (ME) algorithms, adaptive search range (ASR) algorithms are more fundamental, regular and flexible. In variable block size motion estimation (VBSME), ASR algorithms can be applied whether on a whole frame (frame level), or on an entire macroblock which includes up to forty-one blocks (macroblock level), or just on a single block (block level). In the other hand, in H.264/AVC, not the motion vectors (MVs) but the motion vector differences (MVDs) are coded and the median motion vector predictors (median-MVPs) are used to place the search centers. In this sense, it can be thought that the search windows (SWs) are centered at the positions pointed by median-MVPs, the search ranges (SRs) play the role of limiting MVDs. Thus it is reasonable for considering using MVDs to predict SRs. In this paper, one of the MB level and two of the block level, at all three MVD based SR prediction algorithms are proposed. VBSME based experiments are carried out to assess the proposed algorithms. Comparisons between the proposed three algorithms and the previously proposed one given in [8] are done in terms of encoding quality and computational complexity.