High-frequency characterization and delay-time analysis have been performed for a short channel AlGaN/GaN heterojunction FET. The fabricated device with a short gate length (Lg) of 0.07 µm exhibited an extrinsic current gain cutoff frequency of 81 GHz and a maximum frequency of oscillation of 190 GHz with a maximum stable gain (MSG) of 8.2 dB at 60 GHz. A new scheme for the delay-time analysis was proposed, in which the effects of rather large series resistance RS + RD are properly taken into account. By applying the new scheme to a device with Lg=0.25 µm, we obtained an effective high-field electron velocity of 1.75107 cm/s, which is consistent with our previous results calculated using Monte Carlo simulation.

This paper describes amplification with improved linearity by employing a linearizing circuit in an input circuit of an internally-matched Ku-band high power amplifier. The linearizing circuit is composed of series L, C, R and an FET with grounded source and drain, and is connected between the input signal line and ground. This linearizing circuit was applied to a Ku-band 10 W output power amplifier utilizing a 25.2 mm gate-width double-doped Heterojunction FET. The power amplifier demonstrated a 8 dB reduction of the third-order intermodulation at about 6 dB output power backoff point from the 2 dB output compression point.

A buried gate AlGaAs/InGaAs heterojunction FET (HJFET) with gate breakdown voltage of 30 V was examined for high drain bias (higher than 10 V) operation. High breakdown voltage was realized due to the optimization of the narrow recess depth. A 1.4 mm HJFET has exhibited an output power of 30.2 dBm (1050 mW) with 50% power added efficiency (PAE) and 12.1 dB linear gain at 12 GHz with a 13 V drain bias. An internal matching circuit for a 16.8 mm HJFET was designed using a large-signal load impedance determined from load-pull measurement. The 16.8 mm internally-matched HJFET has delivered 38.9 dBm (7.8 W) output power with 46% PAE and 11.6 dB linear gain at 12 GHz with a drain bias of 13 V. This is the first report of higher than 10 V operation of an X- and Ku-band power HJFET with the excellent power performance.

Because of numerous circuit resources of FPGAs, there is a performance gap between FPGAs and ASICs. In this paper, we propose a small-memory logic cell, COGRE, to reduce the FPGA area. Our approach is to investigate the appearance ratio of the logic functions in a circuit implementation. Moreover, we group the logic functions on the basis of the NPN-equivalence class. The results of our investigation show that only small portions of the NPN-equivalence class can cover large portions of the logic functions used to implement circuits. Further, we found that NPN-equivalence classes with a high appearance ratio can be implemented by using a small number of AND gates, OR gates, and NOT gates. On the basis of this analysis, we develop COGRE architectures composed of several NAND gates and programmable inverters. The experimental results show that the logic area of 4-COGRE is smaller than that of 4-LUT and 5-LUT by approximately 35.79% and 54.70%, respectively. The logic area of 8-COGRE is 75.19% less than that of 8-LUT. Further, the total number of configuration memory bits of 4-COGRE is 8.26% less than the number of configuration memory bits of 4-LUT. The total number of configuration memory bits of 8-COGRE is 68.27% less than the number of configuration memory bits of 8-LUT.

This paper describes a high power GaN-FET amplifier which is developed for wideband code division multiple access (W-CDMA) base stations. We design a bias network which is symmetrically arranged to the RF line (two way bias network) in order to reduce impedance at a baseband frequency of the multi-carrier W-CDMA signal. As a result, the amplifier with the two way bias network successfully suppressed memory effects. Therefore, the application of a DPD technique to the GaN-FET amplifier with the two way bias network demonstrates almost 20 dB linearity improvement in IM3 and considerable improvement in higher order IMD, resulting in low IMD of less than -50 dBc at the highest ever reported W-CDMA average output power of 76 W.