Self-dithered digital delta-sigma modulators (DDSMs) are commonly used in fractional-N frequency synthesizers due to their ability to eliminate unwanted spurs from the synthesizer’s spectra without requiring additional hardware. However, when operating with a low-bit input, self-dithered DDSMs can still suffer from spurious tones at certain inputs. In this paper, we propose a self-dithered MASH 1-1-1-1 structure to mitigate the spur issue in the self-dithered MASH DDSMs. The proposed self-dithered MASH 1-1-1-1 suppresses the spurs with shaped dithering and achieves 4th order noise shaping.

In the optimization of decision diagrams, variable reordering approaches are often used to minimize the number of nodes. However, such approaches are less effective for analysis of multi-state systems given by monotone structure functions. Thus, in this paper, we propose algorithms to minimize the number of edges in an edge-valued multi-valued decision diagram (EVMDD) for fast analysis of multi-state systems. The proposed algorithms minimize the number of edges by grouping multi-valued variables into larger-valued variables. By grouping multi-valued variables, we can reduce the number of nodes as well. To show the effectiveness of the proposed algorithms, we compare the proposed algorithms with conventional optimization algorithms based on a variable reordering approach. Experimental results show that the proposed algorithms reduce the number of edges by up to 15% and the number of nodes by up to 47%, compared to the conventional ones. This results in a speed-up of the analysis of multi-state systems by about three times.

We present a privacy preserving method based on inserting dummy data into original data on the data structure called Zero-suppressed BDDs (ZDDs). Our task is distributed itemset mining, which is frequent itemset mining from horizontally partitioned databases stored in distributed places called sites. We focus on the fundamental case in which there are two sites and each site has a database managed by its owner. By dividing the process of distributed itemset mining into the set union and the set intersection, we show how to make the operations secure in the sense of undistinguishability of data, which is our criterion for privacy preserving based on the already proposed criterion, p-indistinguishability. Our method conceals the original data in each operation by inserting dummy data, where ZDDs, BDD-based directed acyclic graphs, are adopted to represent sets of itemsets compactly and to implement the set operations in constructing the distributed itemset mining process. As far as we know, this is the first technique which gives a concrete representation of sets of itemsets and an implementation of set operations for privacy preserving in distributed itemset mining. Our experiments show that the proposed method provides undistinguishability of dummy data. Furthermore, we compare our method with Secure Multiparty Computation (SMC), which is one of the well-known techniques of secure computation.

Channel estimation using data-dependent superimposed training (DDST) is developed to doubly selective channels of Orthogonal Frequency Division Multiplexing (OFDM) systems; it consumes no extra bandwidth. An Inter-carrier interference (ICI) Self-cancelation method based on DDST scheme, IS-DDST, is designed which mitigates the interference from adjacent subcarriers to estimation. Moreover, a dual-iteration detection method is proposed to mitigate the ICI for IS-DDST scheme. Theoretical analysis and simulations show that the proposed scheme can achieve better Mean Square Error (MSE) and Bit Error Ratio (BER) performance than the existing DDST based scheme.

We present an economical and fault-tolerant load balancing strategy (EFTLBS) based on an operator replication mechanism and a load shedding method, that fully utilizes the network resources to realize continuous and highly-available data stream processing without dynamic operator migration over wide area networks. In this paper, we first design an economical operator distribution (EOD) plan based on a bin-packing model under the constraints of each stream bandwidth as well as each server's CPU capacity. Next, we devise super-operator (SO) that load balances multi-degree operator replicas. Moreover, for improving the fault-tolerance of the system, we color the SOs based on a coloring bin-packing (CBP) model that assigns peer operator replicas to different servers. To minimize the effects of input rate bursts upon the system, we take advantage of a load shedding method while keeping the QoS guarantees made by the system based on the SO scheme and the CBP model. Finally, we substantiate the utility of our work through experiments on ns-3.

Digital delta-sigma modulators (DDSMs) applied in fractional-N frequency synthesizers suffer from spurious tones which undermine the synthesizer's spectral purity. We propose a solution featuring no hardware overhead while achieving equivalent spur elimination effect as using LFSR-dithering. This method can be implemented on MASH and single-loop DDSMs of 3rd- and 2nd-order.

This paper proposes a high-speed architecture to realize two-variable numeric functions. It represents the given function as an edge-valued multiple-valued decision diagram (EVMDD), and shows a systematic design method based on the EVMDD. To achieve a design, we characterize a numeric function f by the values of l and p for which f is an l-restricted Mp-monotone increasing function. Here, l is a measure of subfunctions of f and p is a measure of the rate at which f increases with an increase in the dependent variable. For the special case of an EVMDD, the EVBDD, we show an upper bound on the number of nodes needed to realize an l-restricted Mp-monotone increasing function. Experimental results show that all of the two-variable numeric functions considered in this paper can be converted into an l-restricted Mp-monotone increasing function with p=1 or 3. Thus, they can be compactly realized by EVBDDs. Since EVMDDs have shorter paths and smaller memory size than EVBDDs, EVMDDs can produce fast and compact NFGs.

This paper analyzes the spurious sources in DDS synthesizers and deduces the simple model of DDS output signal. The method of feeding pseudo-random noise into the phase accumulator for spurious reduction is discussed. A new method for spurious reduction by compensating for DAC integer nonlinearity is proposed with two DACs and a power combiner. One DAC generates the error signal to compensate for the other DAC INL. The factor how the amplitude error and the phase error between the two combined signals affect the spurious level is also analyzed. The experiment shows that the spurious reduction can be improved by at least 18 dB, which proves the validity of the DAC INL compensation method for the spurious reduction.

Configurable clock is necessary for many applications such as digital communication systems, however, using the conventional direct digital frequency synthesizer (DDS) as a pulse or clock generator may cause jitter problems. People usually employ phase-interpolation approaches to generate a pulse or clock with correct time intervals. This work proposes a new phase-interpolation DDS scheme, which uses the output of the phase accumulator to provide an initial voltage on an integration capacitor by pre-charging in the first phase, and then performs integration operation on the same integration capacitor in the second phase. By using single capacitor integration, the instability of the delay generator existed in the phase-interpolation DDS can be avoided, and the impact caused by capacitance error in the circuit implementation also can be reduced. Furthermore, without ROM tables, the proposed DDS using pre-charging integration not only reduces the spurious level of the clock output, but also has a low hardware complexity.

Numerical function generators (NFGs) realize arithmetic functions, such as ex,sin(πx), and , in hardware. They are used in applications where high-speed is essential, such as in digital signal or graphics applications. We introduce the edge-valued binary decision diagram (EVBDD) as a means of reducing the delay and memory requirements in NFGs. We also introduce a recursive segmentation algorithm, which divides the domain of the function to be realized into segments, where the given function is realized as a polynomial. This design reduces the size of the multiplier needed and thus reduces delay. It is also shown that an adder can be replaced by a set of 2-input AND gates, further reducing delay. We compare our results to NFGs designed with multi-terminal BDDs (MTBDDs). We show that EVBDDs yield a design that has, on the average, only 39% of the memory and 58% of the delay of NFGs designed using MTBDDs.

We propose a new method of logic synthesis for dual-rail RSFQ (rapid single-flux-quantum) digital circuits. RSFQ circuit technology is one of the strongest candidates for the next generation technology of digital circuits. For representing logic functions, we use a root-shared binary decision diagram (RSBDD) which is a directed acyclic graph constructed from binary decision diagrams. In the method, first we construct an RSBDD from given logic functions, and then reduce the number of nodes in the constructed RSBDD by variable re-ordering. Finally, we synthesize a dual-rail RSFQ circuit from the reduced RSBDD. We have implemented the method and have synthesized benchmark circuits. We have synthesized dual-rail circuits that consist of about 27% fewer logic elements than those synthesized by a Transduction-based method on average.

SpecC language is designated to handle the design of entire system from specification to implementation and of hardware/software co-design. Concurrency is one of the features of SpecC which expresses the parallel execution of processes. Describing the systems which contain concurrent behaviors would have some data exchanging or transferring among them. Therefore, the synchronization semantics (notify/wait) of events should be incorporated. The actual design, which is usually sophisticated by its characteristic and functionalities, may contain a bunch of event synchronization codes. This will make the design difficult and time-consuming to verify. In this paper, we introduce a technique which helps verifying the synchronization of events in SpecC. The original SpecC code containing synchronization semantics is parsed and translated into a Boolean SpecC code. The difference decision diagrams (DDDs) is used to verify for event synchronization on Boolean SpecC code. The counter examples for tracing back to the original source are given when the verification results turn out to be unsatisfied. Here we also introduce idea on automatically refinement when the results are unsatisfied and preset some preliminary results.

We propose a new phase interpolator that provides precise fractional phase pulses without the need to adjust circuit constants. The variable phases are produced by detecting the coincidence of two voltages, the ramp wave and the threshold voltage. The new phase interpolator can keep the same ramp wave slope and the same threshold voltage for different output phases. This significantly reduces the power dissipation of the voltage comparator. This phase interpolator can be applied to various timing circuits and clock generators, such as frequency multipliers and direct digital synthesizers. We present a novel frequency doubler, a novel frequency tripler, a direct digital synthesizer (DDS), and a novel wideband DDS (WDDS) as applications of our new phase interpolator, which uses 0.35-mm CMOS process technology. Experimental results confirm the functionarity of the new phase interpolator. An 8-bit complete DDS IC dissipates only 2.1 mA at a 50-MHz clock rate and a supply voltage of 2.8 V.

Functional decomposition is an essential technique of logic synthesis and is important especially for FPGA design. Bertacco and Damiani proposed an efficient algorithm finding simple disjoint decomposition using Binary Decision Diagrams (BDDs). However, their algorithm is not complete and does not find all the decompositions. This paper presents a complete theory of simple disjoint decomposition and describes an efficient algorithm using BDDs.

Manipulation of Boolean functions is one of the most important techniques for implementing of VLSI logic design systems. This paper presents a fast method for generating prime-irredundant covers from Binary Decision Diagrams (BDDs), which are efficient representation of Boolean functions. Prime-irredundant covers are forms in which each cube is a prime implicant and no cube can be eliminated. This new method generates compact cube sets from BDDs directly, in contrast to the conventional cube set reduction algorithms, which commonly manipulate redundant cube sets or truth tables. Our method is based on the idea of a recursive operator, proposed by Morreale. Morreale's algorithm is also based on cube set manipulation. We found that the algorithm can be improved and rearranged to fit BDD operations efficiently. The experimental results demonstrate that our method is efficient in terms of time and space. In practical time, we can generate cube sets consisting of more than 1,000,000 literals from multi-level logic circuits which have never previously been flattened into two-level logics. Our method is more than 10 times faster than ESPRESSO in large-scale examples. It gives quasi-minimum numbers of cubes and literals. This method should find many useful applications in logic design systems.

This paper proposes a high resolution and fast frequency settling PLL synthesizer for frequency hopping radio communication equipment. The proposed synthesizer enables the carrier frequency to be changed within the duration of a burst signal and yields higher frequency resolution than the reference signal frequency. To reduce frequency settling time without degradation of frequency resolution and phase noise, this paper proposes a new phase and frequency preset (PEP) PLL synthesizer which employs a digital phase accumulator to generate high resolution reference signal. Experimental results show that the settling time of a prototype synthesizer is less than 300µs while spurious signals are suppressed by more than 55 dB. In comparison with conventional PLL synthesizers, the frequency settling time is reduced by 80%. Furthermore, the higher frequency resolution than the reference signal is successfully demonstrated. Therefore, the proposed PFP PLL synthesizer with the digital reference signal can achieve the output signal with high frequency resolution less than 1Hz.