In this paper, a design method for the infinite impulse response (IIR) filters using the particle swarm optimization (PSO) is developed. It is well-known that the updating in the PSO tends to stagnate around local minimums due to a strong search directivity. Recently, the asynchronous digenetic PSO with nonlinear dissipative term (N-AD-PSO) has been proposed as a purpose for a diverse search. Therefore, it can be expected that the stagnation can be avoided by the N-AD-PSO. However, there is no report that the N-AD-PSO has been applied to any realistic problems. In this paper, the N-AD-PSO is applied for the IIR filter design. Several examples are shown to clarify the effectiveness and the drawback of the proposed method.

In this paper, we propose a 3rd-order nonlinear IIR filter for compensating nonlinear distortions of loudspeaker systems. Nonlinear distortions are common around the lowest resonance frequency for electrodynamic loudspeaker systems. One interesting approach to compensating nonlinear distortions is to employ a mirror filter. The mirror filter is derived from the nonlinear differential equation for loudspeaker systems. The nonlinear parameters of a loudspeaker system, which include the force factor, stiffness, and so forth, depend on the displacement of the diaphragm. The conventional filter structure, which is called the 2nd-order nonlinear IIR filter that originates the mirror filter, cannot reduce nonlinear distortions at high frequencies because it does not take into account the nonlinearity of the self-inductance of loudspeaker systems. To deal with this problem, the proposed filter takes into account the nonlinearity of the self-inductance and has a 3rd-order nonlinear IIR filter structure. Hence, this filter can reduce nonlinear distortions at high frequencies while maintaining a lower computational complexity than that of a Volterra filter-based compensator. Experimental results demonstrate that the proposed filter outperforms the conventional filter by more than 2dB for 2nd-order nonlinear distortions at high frequencies.

In this paper, we propose a parameter estimation method using Volterra kernels for the nonlinear IIR filters, which are used for the linearization of closed-box loudspeaker systems. The nonlinear IIR filter, which originates from a mirror filter, employs nonlinear parameters of the loudspeaker system. Hence, it is very important to realize an appropriate estimation method for the nonlinear parameters to increase the compensation ability of nonlinear distortions. However, it is difficult to obtain exact nonlinear parameters using the conventional parameter estimation method for nonlinear IIR filter, which uses the displacement characteristic of the diaphragm. The conventional method has two problems. First, it requires the displacement characteristic of the diaphragm but it is difficult to measure such tiny displacements. Moreover, a laser displacement gauge is required as an extra measurement instrument. Second, it has a limitation in the excitation signal used to measure the displacement of the diaphragm. On the other hand, in the proposed estimation method for nonlinear IIR filter, the parameters are updated using simulated annealing (SA) according to the cost function that represents the amount of compensation and these procedures are repeated until a given iteration count. The amount of compensation is calculated through computer simulation in which Volterra kernels of a target loudspeaker system is utilized as the loudspeaker model and then the loudspeaker model is compensated by the nonlinear IIR filter with the present parameters. Hence, the proposed method requires only an ordinary microphone and can utilize any excitation signal to estimate the nonlinear parameters. Some experimental results demonstrate that the proposed method can estimate the parameters more accurately than the conventional estimation method.

The authors have evaluated a method of expanding the bit depth of image signals called SGRAD, which requires fewer calculations, while degrading the sharpness of images less. Where noise is superimposed on image signals, the conventional method for obtaining high bit depth sometimes incorrectly detects the contours of images, making it unable to sufficiently correct the gradation. Requiring many line memories is also an issue with the conventional method when applying the process to vertical gradation. As a solution to this particular issue, SGRAD improves the method of detecting contours with transiting gradation to effectively correct the gradation of image signals which noise is superimposed on. In addition, the use of a prediction algorithm for detecting gradation reduces the scale of the circuit with less correction of the vertical gradation.

In this paper, we propose a rectangular weighting function that can be used in the method of iteratively reweighted least squares (IRWLS) for designing equiripple all-pass IIR filters. The purpose of introducing this weighting function is to improve the convergence performance in the solution of the IRWLS. The height of each rectangle is designed to be equal to the local maximum of each ripple, and the width of each rectangle is designed so that the area of each rectangle becomes equal to the area of each ripple. Here, the ripple is the absolute value of the phase error. We show experimentally that the convergence performance in the solution of the IRWLS can be improved by using the proposed weighting function.

This paper describes a small size broadband fractional-N RF synthesizer for an RF test module with a high throughput and multiple resources installed in RF Automated Test Equipment (ATE) systems. The core device is the PLL-LSI composed of the 13-band asymmetrical tournament form voltage-controlled oscillators (VCOs) and the proposed 48-bit ΔΣ modulator with the infinite impulse response (IIR) filter. The single-loop PLL RF synthesizer is constructed in the form of systems in package (SiP) including the PLL-LSI and the active loop filter. The RF synthesizer SiP features a small size of 20mm × 20mm × 3mm, a high frequency resolution of smaller than 50µHz, and a phase noise of better than -110dBc/Hz at offset frequency of 1MHz across a frequency range of 100MHz to 13.4GHz. In addition, a frequency settling time of 150 µs that is faster than our conventional dual-loop PLL synthesizers using the discrete VCOs or the YIG-tuned oscillators (YTOs) is achieved. The synthesizer SiP significantly contributes to the realization of small size, high throughput RF test modules for RF ATEs.

The Direct Sampling Mixer (DSM) with a complex coefficient transfer function is demonstrated. The operation theory and the detail design methodology are discussed for the high order complex DSM, which can achieve large image rejection ratio by introducing the attenuation pole at the image frequency band. The proposed architecture was fabricated in a 65 nm CMOS process. The measured results agree well with the theoretical calculation, which proves the validity of the proposed architecture and the design methodology. By using the proposed design method, it will be possible for circuit designers to design the DSM with large image rejection ratio without repeated lengthy simulations.

Repeaters equipped with on-board digital baseband processing in a time division duplex (TDD) demand short processing time in order to alleviate inter-symbol interference resulting from having a time delay that is greater than the guard time. To accomplish this, the total system delay of the repeater should be minimized as much as possible without distorting signal quality. Conventionally, the finite impulse response (FIR) type of filter is deployed as a channelization filter, but due to the necessity of large numbers of coefficients to fulfill a prerequisite filter response with a sharp transition band characteristic, an unwanted excessive time delay intrinsically occurs. To make the processing delay as low as possible, this paper proposes a method employing a minimum-phase characterized infinite impulse response (IIR) filter whose magnitude response is almost identical to that of the original FIR filter. Furthermore, in order to linearize the phase response of the designed IIR filter, this paper also introduces an all-pass filter cascaded with the IIR filter for digital down-conversion as well as up-conversion. To achieve further simplicity, this paper introduces polyphase-style IIR filters transformed from conventional single IIR filters that have their own all-pass filters in order to linearize the phase response. The computer simulation results verify that the proposed integrated IIR filter exhibits a relatively short processing delay with a minor deterioration in signal quality-like error vector magnitude (EVM) performance.

This paper proposes a synthesis method of 2-channel IIR paraunitary filter banks by successive extraction of 2-port lattice sections. When a power symmetry transfer function is given, a filter bank is realized as cascade of paraunitary 2-port lattice sections. The method can synthesize both odd- and even-order filters with Butterworth or elliptic characteristics. The number of multiplications per second can also be reduced.

This paper presents the regulation and dynamic characteristics of the dc-dc converter with digital PID control, the minimum phase FIR filter or the IIR filter, and then the design criterion to improve the dynamic characteristics is discussed. As a result, it is clarified that the DC-DC converter using the IIR filter method has superior performance characteristics. The regulation range is within 1.3%, the undershoot against the step change of the load is less than 2% and the transient time is less than 0.4 ms with the IIR filter method. In this case, the switching frequency is 100 kHz and the step change of the load R is from 50 Ω to 10 Ω . Further, the superior characteristics are obtained when the first gain, the second gain and the second cut-off frequency are relatively large, and the first cut-off frequency and the passing frequency are relatively low. Moreover, it is important that the gain strongly decreases at the second cut-off frequency because the upper band pass frequency range must be always less than half of the sampling frequency based on the sampling theory.

In this paper, we propose designing method for separable-denominator two-dimensional Infinite Impulse Response (IIR) filters (separable 2D IIR filters) by Successive Projection (SP) methods using the stability criteria based on the system matrix. It is generally known that separable 2D IIR filters are stable if and only if each of the denominators is stable. Therefore, the stability criteria of 1D IIR filters can be used for separable 2D IIR filters. The stability criteria based on the system matrix are a necessary and sufficient condition to guarantee stability in 1D IIR filters. Therefore, separable 2D IIR filters obtained by the proposed design method have a smaller error ripple than those obtained by the conventional design method using the stability criterion of Rouche's theorem.

Usually an FIR filter is used to model the physical paths in an active noise control system. However, the order of the filter to be modeled is a key factor for determining the computational load for the adaptive algorithms associated with active noise control (ANC), particularly for multi-channel algorithms. In this letter, the relationships among the filter's order, the plant modeling error and the location of poles for the transfer functions of the physical paths in an ANC system are theoretically examined and numerical examples are given to verify the theoretical results.

A reduced-sample-rate (RSR) sigma-delta-pipeline (SDP) analog-to-digital converter architecture suitable for high-resolution and high-speed applications with low oversampling ratios (OSR) is presented. The proposed architecture employs a class of high-order noise transfer function (NTF) with a novel pole-zero locations. A design methodology is developed to reach the optimum NTF. The optimum NTF determines the location of the non-zero poles improving the stability of the loop and implementing the reduced-sample-rate structure, simultaneously. Unity gain signal transfer function to mitigate the analog circuit imperfections, simplified analog implementation with reduced number of operational transconductance amplifiers (OTAs), and novel, aggressive yet stable NTF with high out of band gain to achieve larger peak signal-to-noise ratio (SNR) are the main features of the proposed NTF and ADC architecture. To verify the usefulness of the proposed architecture, NTF, and design methodology, two different cases are investigated. Simulation results show that with a 4th-order modulator, designed making use of the proposed approach, the maximum SNDR of 115 dB and 124.1 dB can be achieved with only OSR of 8, and 16 respectively.

This paper presents a novel class of sigma-delta modulator topologies for low-voltage, high-speed, and high-resolution applications with low oversampling ratios (OSRs). The main specifications of these architectures are the reduced analog circuit requirements, large out-of-band gain in the noise transfer function (NTF) without any stability concerns to achieve high signal to noise ratio (SNR) with a low OSR, and unity-gain signal transfer function (STF) to reduce the harmonic distortions resulted from the analog circuit imperfections. To demonstrate the efficiency of the proposed modulator architectures a prototype with HSPICE is implemented. A low-power two-stage class A/AB OTA with modified common mode feedback (CMFB) circuit in the first stage is used to implement the fourth order modulator. Simulation results with OSR of 16 give signal to noise plus distortion ratio (SNDR) and dynamic range (DR) of 90-dB and 92.5-dB including the circuit noise in the 1.25-MHz signal bandwidth, respectively. The circuit is implemented in a 0.13-µm standard CMOS technology. It dissipates about 40-mW from a single 1.2-V power supply voltage.

In this paper, we propose a simple method to find the optimal rational function, with a fixed denominator, which minimizes an integral of polynomially weighted squared error to given analytic function. Firstly, we present a generalization of the Walsh's theorem. By using the knowledge on the zeros of the fixed denominator, this theorem characterizes the optimal rational function with a system of linear equations on the coefficients of its numerator polynomial. Moreover when the analytic function is specially given as a polynomial, we show that the optimal numerator can be derived without using any numerical integration or any root finding technique. Numerical examples demonstrate the practical applicability of the proposed method.

This paper proposes a design method of 2-D variable IIR digital filters with high frequency tuning accuracy. In the proposed method, a parallel complex allpass structure is used as the prototype structure of the 2-D variable digital filters in order to obtain low sensitivity characteristic. Because the proposed 2-D variable digital filter is composed of first-order complex allpass sections connected in parallel, the proposed variable digital filter possesses several advantages such as low sensitivity characteristic in the passband, simple stability monitoring and high parallelism. In order to improve the frequency tuning accuracy of the proposed variable digital filter, each first-order complex allpass section is substituted by a new first-order complex allpass section with low sensitivity characteristic. Moreover, the coefficient sensitivity analysis of a 2-D parallel complex allpass structure is presented. Numerical examples show that the proposed 2-D variable IIR digital filter has high tuning accuracy under the finite coefficient wordlength.

A new approach to design variable IIR digital filters by using a cascade of N identical individual filters of any order n is proposed in this paper. First, the approximation method for lowpass filter specifications is outlined, then the general limitations of the new method are investigated and a compact formula is derived. Next, the limitations for the main canonic approximations (Butterworth, Chebyshev and Elliptic) are investigated and compared and convenient expressions for design and evaluation are obtained. New first- and second-order filter sections, permitting very easy tuning of the cutoff frequency by recalculating and reprogramming of a single multiplier coefficient value, are developed and the design and tuning strategies for highpass, bandpass and bandstop filters are proposed. Finally design examples are given and the sound superiority of the new method compared to other known is demonstrated experimentally.

The adaptive system design by 16-bit fixed point processing enables to employ an inexpensive digital signal processor (DSP). The narrow dynamic range of such 16 bits, however, does not guarantee the same performance that is confirmed beforehand by computer simulations. A cause of degrading the performance originates in the operation halving the word length doubled by multiplication. This operation rounds off small signals staying in the lower half of the doubled word length to zero. This problem can be solved by limiting the multiplier to only its sign () like the signed regressor algorithm, named 'bi-quantized-x' algorithm in this paper, for the convenience mentioned below. This paper first derives the equation describing the convergence property provided by a type of signed regressor algorithms, the bi-quantized-x normalized least mean square (NLMS) algorithm, and then formulates its convergence condition and the step size maximizing the convergence rate. This paper second presents a technique to improve the convergence property. The bi-qiantized-x NLMS algorithm quantizes the reference signal to 1 according to the sign of the reference signal, whereas the technique moreover assigns zero to the reference signal whose amplitude is less than a predetermined level. This paper explains the principle that the 'tri-qunatized-x' NLMS algorithm employing the technique can improve the convergence property, and confirms the improvement effect by computer simulations.

This paper proposes distributed evolutionary digital filters (EDFs) as an improved version of the original EDF. The EDF is an adaptive digital filter which is controlled by adaptive algorithm based on evolutionary computation. In the proposed method, a large population of the original EDF is divided into smaller subpopulations. Each sub-EDF has one subpopulation and executes the small-sized main loop of the original EDF. In addition, the distributed algorithm periodically selects promising individuals from each subpopulation. Then, they migrate to different subpopulations. Numerical examples show that the distributed EDF has a higher convergence rate and smaller steady-state value of the square error than the LMS adaptive digital filter, the adaptive digital filter based on the simple genetic algorithm and the original EDF.

We present a new family of algorithms that solve the bias problem in the equation-error based adaptive infinite impulse response (IIR) filtering. A novel constraint, called the constant-norm constraint, unifies the quadratic constraint and the monic one. By imposing the monic constraint on the mean square error (MSE) optimization, the merits of both constraints are inherited and the shortcomings are overcome. A new cost function based on the constant-norm constraint and Lagrange multiplier is defined. Minimizing the cost function gives birth to a new family of bias-free adaptive IIR filtering algorithms. For example, two efficient algorithms belonging to the family are proposed. The analysis of the stationary points is presented to show that the proposed methods can indeed produce bias-free parameter estimates in the presence of white noise. The simulation results demonstrate that the proposed methods indeed produce unbiased parameter estimation, while being simple both in computation and implementation.