Recent years have seen a general resurgence of interest in analog signal processing and computing architectures. In addition, extensive theoretical and experimental literature on chaos and analog chaotic oscillators exists. One peculiarity of these circuits is the ability to generate, despite their structural simplicity, complex spatiotemporal patterns when several of them are brought towards synchronization via coupling mechanisms. While by no means a systematic survey, this paper provides a personal perspective on this area. After briefly covering design aspects and the synchronization phenomena that can arise, a selection of results exemplifying potential applications is presented, including in robot control, distributed sensing, reservoir computing, and data augmentation. Despite their interesting properties, the industrial applications of these circuits remain largely to be realized, seemingly due to a variety of technical and organizational factors including a paucity of design and optimization techniques. Some reflections are given regarding this situation, the potential relevance to discontinuous innovation in analog circuit design of chaotic oscillators taken both individually and as synchronized networks, and the factors holding back the transition to higher levels of technology readiness.

A high-image-rejection wireless receiver with an N-phase active RC complex filter is proposed and analyzed. Signal analysis shows that the double-conversion receiver with (N+N2) mixers corrects the gain and phase mismatches of the adjacent image. Monte Carlo simulations evaluate the relation between image-rejection performances and the dispersions of device parameters for the double-conversion wireless receiver. The Monte Carlo simulations show that the image rejection ratio of the adjacent image depends almost only on R and C mismatches in the complex filter.

Majority logic is quite important for various applications such as fault tolerant systems, threshold logic, spectrum spread coding, and artificial neural networks. The circuit implementation of majority logic is difficult when the number of inputs becomes large because the number of transistors becomes huge and serious delay would occur. In this paper, we propose a new majority circuit with large fan-in. The circuit is composed of ordinary CMOS transistors and the total number of transistors is approximately only 4N, where N is the total number of inputs. We confirmed a correct operation by using HSPICE simulation. The yield of the proposed circuit was evaluated with respect to N under the variations of device parameters by using Monte Carlo simulation.

In this study, a well-shaped microelectrode array (MEA) for fabricating a high-density complementary metal-oxide semiconductor amperometric electrochemical sensor array was designed and verified. By integrating an auxiliary electrode with the well-shaped structure of the MEA, the footprint was reduced and high density and high resolution were also achieved. The results of three-dimensional electrochemical simulations confirmed the effectiveness of the proposed MEA structure and possibility of increasing the density to four times than that achieved by the conventional two-dimensional structure.

An energy-efficient ΔΣ modulator using a novel switched-capacitor-based integrator has been investigated. The proposed dynamic integrator uses a common-source configuration, where a MOSFET turns off after the charge redistribution is completed. Thus, only the subthreshold current flows through the integrator, resulting in high energy efficiency. A constant threshold voltage works as the virtual ground in conventional opamp-based integrators. The performance has been estimated for a 2nd-order ΔΣ modulator by transistor-level circuit simulation assuming a 0.18-µm standard CMOS technology. An FOM of 29fJ/conv-step was obtained with a peak SNDR of 82.6dB for a bandwidth and a sampling frequency of 20kHz and 5MHz, respectively.

To improve immunity against process gradients, a common centroid constraint, in which every pair of capacitors should be placed symmetrically with respect to a common center point, is widely used. The pair of capacitors are derived by dividing some original capacitors into two halves. Xiao et al. proposed a method to obtain a placement which satisfies the common centroid constraints, but this method has a defect. In this paper, we propose a decoding algorithm to obtain a placement which satisfies common centroid constraints.

Recent attempts to directly combine CMOS pixel readout chips with modern gas detectors open the possibility to fully take advantage of gas detectors. Those conventional readout LSIs designed for hybrid semiconductor detectors show some issues when applied to gas detectors. Several new proposed readout LSIs can improve the time and the charge measurement precision. However, the widely used basic charge sensitive amplifier (CSA) has an almost fixed dynamic range. There is a trade-off between the charge measurement resolution and the detectable input charge range. This paper presents a method to apply the folding integration technique to a basic CSA. As a result, the detectable input charge dynamic range is expanded while maintaining all the key merits of a basic CSA. Although folding integration technique has already been successfully applied in CMOS image sensors, the working conditions and the signal characteristics are quite different for pixel readout LSIs for gas particle detectors. The related issues of the folding CSA for pixel readout LSIs, including the charge error due to finite gain of the preamplifier, the calibration method of charge error, and the dynamic range expanding efficiency, are addressed and analyzed. As a design example, this paper also demonstrates the application of the folding integration technique to a Qpix readout chip. This improves the charge measurement resolution and expands the detectable input dynamic range while maintaining all the key features. Calculations with SPICE simulations show that the dynamic range can be improved by 12 dB while the charge measurement resolution is improved by 10 times. The charge error during the folding operation can be corrected to less than 0.5%, which is sufficient for large input charge measurement.

This letter proposes an analog active noise control (ANC) circuit with an all-pass filter (APF). To improve performance of the previously reported analog ANC circuit, we inserted an APF to the circuit in order to fit phases of a noise and an electrical signal in the circuit. As a result, we confirmed improvement of the noise canceling effect of the analog ANC circuit.

This paper describes the analysis and design of low-noise analog circuits for a new architecture readout LSI, Qpix. In contrast to conventional readout LSIs using TOT method, Qpix measures deposited charge directly as well as time information. A preamplifier with a two-stage op amp and current-copy output buffers is proposed to realize these functions. This preamplifier is configured to implement a charge sensitive amplifier (CSA) and a trans-impedance amplifier (TIA). Design issues related to CSA are analyzed, which includes gain requirement of the op amp, stability and compensation of the two-stage cascode op amp, noise performance estimation, requirement for the resolution of the ADC and time response. The offset calibration method in the TIA to improve the charge detecting sensitivity is also presented. Also, some design principles for these analog circuits are presented. In order to verify the theoretical analysis, a 400-pixel high speed readout LSI: Qpix v.1 has been designed and fabricated in 180 nm CMOS process. Calculations and SPICE simulations show that the total output noise is about 0.31 mV (rms) at the output of the CSA and the offset voltage is less than 4 mV at the output of the TIA. These are attractive performances for experimental particle detector using Qpix v.1 chip as its readout LSI.

In this letter, we describe a low power current to time converter for wireless sensor networks. The proposed circuit has some advantages of high linearity and wide measurement range. From the evaluation using HSPICE with 0.18 µm CMOS device parameters, the output differential error for the input current variation is approximately 0.1 µs/nA under the condition that the current is varied from 100 nA to 500 nA. The idle power consumption is approximately zero.

Along with the miniaturization of CMOS-LSIs, control methods for LSIs have been extensively developed. The most predominant method is to digitize observed values as early as possible and to use digital control. Thus, many types of analog-to-digital converters (ADCs) have been developed such as temperature, time, delay, and frequency converters. ADCs are the easiest circuits into which digital correction methods can be introduced because their outputs are digital. Various types of calibration method have been developed, which has markedly improved the figure of merits by alleviating margins for device variations. The above calibration and correction methods not only overcome a circuit's weak points but also give us the chance to develop quite new circuit topologies and systems. In this paper, several digital calibration and correction methods for major analog-to-digital converters are described, such as pipelined ADCs, delta-sigma ADCs, and successive approximation ADCs.

This study formulates and solves the wire planning problem with electro-migration and interference using an effective integer linear programming (ILP)-based approach. For circuits without obstacles, the proposed approach obtains a wire planning with the minimum wiring area. An effective approach for estimating the length of feasible routing wire is proposed to handle circuits with obstacles. In addition, the space reservation technique, which allocates the ring of the free silicon space around obstacles, is presented to improve interference among routing wires and on-obstacle wires. For circuits with obstacles, the proposed method minimizes total wiring area and reduces interference. Experimental results show that the integer linear-programming-based approach effectively and efficiently minimizes wiring area of routing wires.

Progress of roles and schemes of calibration techniques in data converters are reviewed. Correction techniques of matching error and nonlinearity in analog circuits have been developed by digital assist using high-density and low-power digital circuits. The roles of the calibration are not only to improve accuracy but also to reduce power dissipation and chip area. Among various calibration schemes, the background calibration has significant advantages to achieve robustness to fast ambient change. Firstly the nonlinearity calibrations for pipeline ADCs are reviewed. They have required new solutions for redundancy of the circuits, an error estimation algorithm and reference signals. Currently utilizing the calibration techniques, the performance of 100 Msps and 12 bit has been achieved with 10 mW power dissipation. Secondly the background calibrations of matching error in flash ADC and DAC with error feedback to the analog circuits are described. The flash ADC utilizes the comparator offset correction with successive approximation algorithm. The DAC adopts a self current matching scheme with an analog memory. Measured dissipation power of the ADC is 0.38 mW at 300 MHz clock. Effects of the background calibration to suppress crosstalk noise are also discussed.

A neuro fuzzy method to design analog circuits is explained, where the universe of discourse of the fuzzy system is adjusted by means of a self-organized artificial neural network. As an example of this approach, an op-amp is optimized in order to hold a predetermined aim; where the unity gain bandwidth is an objective of design, and the restrictions of open-loop gain and margin phase are treated as objectives too. Firstly, the experience of the behavior of the circuit is obtained, hence an inference system is constructed and a neural network is applied to achieve a faster convergence into a desired solution. This approach is characterized by having a simple implementation, a very natural understanding and a better performance than static methods of fuzzy optimization.

This paper reports a current-reused pseudo-differential (CRPD) programmable gain amplifier (PGA) that demonstrates small size, low power, wide band, low noise, and high linearity operation with 4 control bits. Implemented in 0.18um CMOS technology, the PGA shows the gain range from -9.9 to 8.3 dB with gain error of less than 0.38 dB. The IIP3, P1 dB, and smallest 3-dB bandwidth are 10.5 to 27 dBm, -9 to 9.5 dBm, and 250 MHz, respectively. The PGA occupies the chip area of 0.04 mm2 and consumes only 460 µA from a 1.2 V supply.

An analog circuit testing scheme is presented. The testing technique is a sinusoidal fault signature characterization, involving the measurement of DC offset, amplitude, frequency and phase shift, and the realization of two crossing level voltages. The testing system is an extension of the IEEE 1149.4 standard through the modification of an analog boundary module, affording functionalities for both on-chip testing capability, and accessibility to internal components for off-chip testing. A demonstrating circuit-under-test, a 4th-order Gm-C low-pass filter, and the proposed analog testing scheme are implemented in a physical level using 0.18-µm CMOS technology, and simulated using Hspice. Both catastrophic and parametric faults are potentially detectable at the minimum parameter variation of 0.5%. The fault coverage associated with CMOS transconductance operational amplifiers and capacitors are at 94.16% and 100%, respectively. This work offers the enhancement of standardizing test approach, which reduces the complexity of testing circuit and provides non-intrusive analog circuit testing.

An all CMOS variable gain amplifier (VGA) which features wide dB-linear gain range per stage (45 dB), low power consumption (1.32 mW), small chip size (0.13 mm2), and low supply voltage (1.2 V) is described. The dB-linear range is extended by reducing the supply voltage of the conventional V-to-I converter. The two-stage VGA implemented in 0.18 µm CMOS offers 90 dB of gain variation, 3 dB bandwidth of greater than 21 MHz, and max/min input IP3 and P1 dB, respectively, of -5/-42 and -12/-50 dBm.

This paper discusses issues in the design of analog-to-digital converters (ADCs) in nanoscale CMOS and introduces some experimental designs incorporating techniques to solve these issues. Technology scaling increases the maximum conversion rate, but it decreases the gain and the SNR. To maintain a high SNR level despite the low-voltage operation, the power consumption needs to be increased. Because of lowered supply voltages, the design of circuits based on operational amplifiers (OpAmps) has become more difficult. Designs without OpAmps have therefore received more attention. One way of realizing low-voltage pipeline ADCs is by using comparator-controlled current sources, instead of conventional OpAmps. Furthermore, successive approximation ADCs and sub-ranging ADCs do not require OpAmps and are therefore suitable for low-voltage operation. ADC designers are now searching for suitable architectures for future nanoscale CMOS processes.

This paper presents an automated design of analog circuits starting with idealized elements. Our system first synthesizes circuits using idealized elements by a genetic algorithm (GA). GA evolves circuit topologies and transconductances of idealized elements to achieve the given specifications. The use of idealized elements effectively reduces search space and make the synthesis efficient. Second, idealized elements in a generated circuit are replaced by MOSFETs. Through the two processes, a circuit satisfying the given specifications can be obtained. The capability of this method was demonstrated through experiments of synthesis of a trans-impedance amplifier and a cubing circuit and benchmark tests. The results of the benchmark tests show the proposed CAD is more than 10 times faster than the CAD which does not use idealized elements.

A LC oscillator based upon the quadrature magnetic coupling to generate a mutual negative resistance (mu-R) is introduced. The topology offers enhanced optimum phase noise at low supply voltages by enabling extended circuit operation in the current-limited regime through the control of its mutual inductors' coupling factor, k. The principal operation of the mu-R oscillator is described and its comparison with the popular cross-coupled topology is discussed. The capability of the technique is demonstrated via design examples of 1.8 GHz oscillators. Simulations show that, by employing inductors with a self-inductance of 2 nH, a quality factor of about 7.5 and a coupling k=0.52, the mu-R oscillator exhibits the minimum phase noise of -142 dBc/Hz at 3 MHz-offset with 18 mA bias current and 2 V supply. This is 3-dB more than the minimum achievable phase noise in the cross-coupled oscillator with identical component parameters and supply voltage level.