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Superconducting detectors have been shown to be superior to other techniques in some applications. However, superconducting devices have not been used for detecting neutrons often in the past decades. We have been developing various superconducting neutron detectors. In this paper, we review our attempts to measure neutrons using superconducting stripline detectors with DC bias currents. These include attempts with a MgB2-based detector and a Nb-based detector with a 10B converter.
Byungjoon KIM Duksoo KIM Youngjoon LIM Dooheon YANG Sangwook NAM Jae-Hoon SONG
This paper proposes a high clutter-rejection technique for wall-penetrating frequency-modulated continuous-wave (FMCW) radar. FMCW radars are widely used, as they moderate the receiver saturation problem in wall-penetrating applications by attenuating short-range clutter such as wall-clutter. However, conventional FMCW radars require a very high-order high-pass filter (HPF) to attenuate short-range clutter. A delay-line (DL) is exploited to overcome this problem. Time-delay shifts beat frequencies formed by reflection waves. This means that a proper time-delay increases the ratio of target-beat frequency to clutter-beat frequency. Consequently, low-order HPF fully attenuates short-range clutter. A third-order HPF rejects more than 20 dB and 30 dB for clutter located at 6 m and 3 m, respectively, with a target located at 9 m detection with a 10,000 GHz/s chirp rate and a 28 ns delay-line.
Yusuke NASU Yohei SAKAMAKI Kuninori HATTORI Shin KAMEI Toshikazu HASHIMOTO Takashi SAIDA Hiroshi TAKAHASHI Yasuyuki INOUE
We present a full description of a polarization-independent athermal differential quadrature phase shift keying (DQPSK) demodulator that employs silica-based planar lightwave circuit (PLC) technology. Silica-based PLC DQPSK demodulator has good characteristics including low polarization dependence, mass producibility, etc. However delay line interferometer (DLI) of demodulator had the large temperature dependence of its optical characteristics, so it required large power consumption to stabilize the chip temperature by the thermo-electric cooler (TEC). We previously made a quick report about an athermal DLI to reduce a power consumption by removing the TEC. In this paper, we focus on the details of the design and the fabrication method we used to achieve the athermal characteristics, and we describe the thermal stability of the signal demodulation and the reliability of our demodulator. We described two athermalization methods; the athermalization of the transmission spectrum and the athermalization of the polarization property. These methods were successfully demonstrated with keeping a high extinction ratio and a small footprint by introducing a novel interwoven DLI configuration. This configuration can also limit the degradation of the polarization dependent phase shift (PDf) to less than 1/10 that with the conventional configuration when the phase shifters on the waveguide are driven. We used our demodulator and examined its demodulation performance for a 43 Gbit/s DQPSK signal. We also verified its long-term reliability and thermal stability against the rapid temperature change. As a result, we confirmed that our athermal demodulator performed sufficiently well for use in DQPSK systems.
We propose an asynchronous variable-length optical packet switch that is based on a packet compression scheme and delay-line loop buffers, and evaluate the packet loss probability of the proposed switch through simulation and analysis. Simulation results well the analytical results and show the accuracy of our analysis. When the packet compression ratio is low, optical packet interval regulators are useful to improve the packet loss probability characteristics.
Shafiul AZAM Takashi YASUI Kaname JINGUJI
This paper presents a method for synthesizing a coherent 1-input 3-output optical delay-line circuit with N stages that is composed of 2(N + 1) directional couplers, N optical delay-lines, 2(N + 1) phase shifters and one external phase shifter with phase value φc . The path difference is equal to the delay time difference Δτ. Synthesis algorithm is based on the division of the transfer matrix into basic component transfer matrices and factorization is completed by repeated size-reduction. A set of recursion equations are also defined to obtain the unknown circuit parameters. In the developed method, it is shown that (13) optical delay-line circuit has the same transmission characteristics as finite impulse response (FIR) digital filters with complex expansion coefficients. Band-pass flat group delay type filter is considered as an example in this paper. It is also confirmed that developed (13) optical delay-line circuit can realize 100% power transmittance.
Tetsuya KAWANISHI Masayuki IZUTSU
We investigated a tunable delay-line using an optical single-sideband modulator and an optical fiber loop. The single-sideband modulator consists of four optical modulators and an RF electric signal source. The fiber loop has a fiber Bragg grating and a couple of optical circulators. The number of times light circulates in the loop depends on the frequency of the rf-signal fed to the modulators. By using numerical simulations, we discussed the deformation of the waveform in the delay-line due to the fiber Bragg gratings, the modulators and the optical amplifiers put in the loop.
Yasushi TAKATORI Keizo CHO Kentaro NISHIMORI Toshikazu HORI
This paper proposes a new digital beamforming adaptive array antenna (DBFAAA) that is effective in severe multipath environments in which timing and carrier synchronization circuits cannot function ideally resulting in the DBFAAA losing control. The proposed DBFAAA has two stages. In the first, the DBFAAA captures the desired signal and establishes synchronization. In the second, the DBFAAA optimizes the beam pattern of the signal. The proposed configuration employs an eigenvector beam of the maximum eigenvalue in the first stage beam-forming. In addition, a fractionally-spaced-tapped-delay-line (FS-TDL) with real tap weights, which is placed after the beam-former, is applied to achieve timing synchronization. The behavior of the proposed DBFAAA for asynchronous sampling data is investigated and the results indicate that the proposed configuration enables asynchronous sampling at the A/D converter. A prototype of the proposed DBFAAA achieving 38-Mbps real-time data communication is introduced and the transmission performance is shown.