A novel displacement sensor was proposed based on a frequency delta-sigma modulator (FDSM) employing a microwave oscillator. To demonstrate basic operation, we fabricated a stylus surface profiler using a cylindrical cavity resonator, where one end of the cavity is replaced by a thin metal diaphragm with a stylus probe tip. Good surface profile was successfully obtained with this device. A 10 nm depth trench was clearly observed together with a 10 µm trench in a single scan without gain control. This result clearly demonstrates an extremely wide dynamic range of the FDSM displacement sensors.

This paper presents a 6th-order quadrature bandpass delta sigma AD modulator (QBPDSM) with 2nd-order image rejection using dynamic amplifier and noise coupling (NC) SAR quantizer embedded by passive adder for the application of wireless communication system. A novel complex integrator using dynamic amplifier is proposed to improve the energy efficiency of the QBPDSM. The NC SAR quantizer can realize an additional 2nd-order noise shaping and 2nd-order image rejection by the digital domain noise coupling technique. As a result, the 6th-order QBPDSM with 2nd-order image rejection is realized by two complex integrators using dynamic amplifier and the NC SAR quantizer. The SPICE simulation results demonstrate the feasibility of the proposed QBPDSM in 90nm CMOS technology. Simulated SNDR of 76.30dB is realized while a sinusoid -3.25dBFS input is sampled at 33.3MS/s and the bandwidth of 2.083MHz (OSR=8) is achieved. The total power consumption in the modulator is 6.74mW while the supply voltage is 1.2V.

A continuous-time (CT) ΔΣ analog-to-digital converter (ADC) is a high resolution, wide-bandwidth ADC. A Gm-C filter is suitable for low power consumption and its frequency characteristics for a loop filter of the ADC. However, in practice, distortion generated in the Gm-C filter degrades the SNDR of the ADC, therefore a high-linearity Gm-cell with low power consumption is needed. A flipped voltage follower (FVF) Gm-cell is also used as a high-linearity Gm-cell, but distortion is caused by variation of drain-source voltage of its input transistors. In this paper, a new high-linearity Gm-cell is proposed for the CT ΔΣ ADC in order to address this problem. A proposed topology is a combination of a FVF and a cascode topology. The inserted transistors in the proposed Gm-cell behave as cascode transistors, therefore the drain-source voltage variation of the input transistor and a PMOS transistor for current source which causes distortion is suppressed. Simulation results show the proposed Gm-cell can realize the same linearity as the conventional Gm-cell with reducing 36% power consumption. A 20MHz-bandwidth CT ΔΣ ADC employing the proposed Gm-cells achieves SNDR of 72.4dB with power consumption of 6.8mW. Active area and FoM of the ADC are, respectively, 250μm × 220μm and 50fJ/conv.-step in 65nm CMOS process.

This paper presents a low distortion 3rd-order continuous-time delta-sigma modulator for a worldwide digital TV-receiver whose peak SNDR is 69.8 dB and SNR is 70.2 dB under 1 V power supply. To enhance SNDR performance, the mechanisms to occur harmonic distortions at feedback current-steering DAC and flash ADC have been analyzed. A low power tuning system using RC-relaxation oscillator has been developed in order to achieve high yield against PVT variations. A 3rd-order modulator with modified single opamp resonator contributes to cost reduction by realizing a very compact circuit. Reduction schemes of the distortions enabled the modulator to achieve FOM of 0.18 pJ/conv-step.