A 72.4dB-SNDR 20MHz-Bandwidth Continuous-Time ΔΣ ADC with High-Linearity Gm-Cells

Tohru KANEKO; Yuya KIMURA; Masaya MIYAHARA; Akira MATSUZAWA

doi:10.1587/transele.E101.C.197

A 72.4dB-SNDR 20MHz-Bandwidth Continuous-Time ΔΣ ADC with High-Linearity Gm-Cells

Tohru KANEKO, Yuya KIMURA, Masaya MIYAHARA, Akira MATSUZAWA

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A continuous-time (CT) ΔΣ analog-to-digital converter (ADC) is a high resolution, wide-bandwidth ADC. A Gm-C filter is suitable for low power consumption and its frequency characteristics for a loop filter of the ADC. However, in practice, distortion generated in the Gm-C filter degrades the SNDR of the ADC, therefore a high-linearity Gm-cell with low power consumption is needed. A flipped voltage follower (FVF) Gm-cell is also used as a high-linearity Gm-cell, but distortion is caused by variation of drain-source voltage of its input transistors. In this paper, a new high-linearity Gm-cell is proposed for the CT ΔΣ ADC in order to address this problem. A proposed topology is a combination of a FVF and a cascode topology. The inserted transistors in the proposed Gm-cell behave as cascode transistors, therefore the drain-source voltage variation of the input transistor and a PMOS transistor for current source which causes distortion is suppressed. Simulation results show the proposed Gm-cell can realize the same linearity as the conventional Gm-cell with reducing 36% power consumption. A 20MHz-bandwidth CT ΔΣ ADC employing the proposed Gm-cells achieves SNDR of 72.4dB with power consumption of 6.8mW. Active area and FoM of the ADC are, respectively, 250μm × 220μm and 50fJ/conv.-step in 65nm CMOS process.

Publication: IEICE TRANSACTIONS on Electronics Vol.E101-C No.4 pp.197-205

Publication Date: 2018/04/01

Publicized

Online ISSN: 1745-1353

DOI: 10.1587/transele.E101.C.197

Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design — Architecture, Circuit, Device and Design Methodology)

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Authors

Tohru KANEKO
  Tokyo Institute of Technology
Yuya KIMURA
  Tokyo Institute of Technology
Masaya MIYAHARA
  Tokyo Institute of Technology
Akira MATSUZAWA
  Tokyo Institute of Technology

Keyword

delta sigma modulator, CMOS, high linearity

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Tohru KANEKO, Yuya KIMURA, Masaya MIYAHARA, Akira MATSUZAWA, "A 72.4dB-SNDR 20MHz-Bandwidth Continuous-Time ΔΣ ADC with High-Linearity Gm-Cells" in IEICE TRANSACTIONS on Electronics, vol. E101-C, no. 4, pp. 197-205, April 2018, doi: 10.1587/transele.E101.C.197.
Abstract: A continuous-time (CT) ΔΣ analog-to-digital converter (ADC) is a high resolution, wide-bandwidth ADC. A Gm-C filter is suitable for low power consumption and its frequency characteristics for a loop filter of the ADC. However, in practice, distortion generated in the Gm-C filter degrades the SNDR of the ADC, therefore a high-linearity Gm-cell with low power consumption is needed. A flipped voltage follower (FVF) Gm-cell is also used as a high-linearity Gm-cell, but distortion is caused by variation of drain-source voltage of its input transistors. In this paper, a new high-linearity Gm-cell is proposed for the CT ΔΣ ADC in order to address this problem. A proposed topology is a combination of a FVF and a cascode topology. The inserted transistors in the proposed Gm-cell behave as cascode transistors, therefore the drain-source voltage variation of the input transistor and a PMOS transistor for current source which causes distortion is suppressed. Simulation results show the proposed Gm-cell can realize the same linearity as the conventional Gm-cell with reducing 36% power consumption. A 20MHz-bandwidth CT ΔΣ ADC employing the proposed Gm-cells achieves SNDR of 72.4dB with power consumption of 6.8mW. Active area and FoM of the ADC are, respectively, 250μm × 220μm and 50fJ/conv.-step in 65nm CMOS process.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/transele.E101.C.197/_p

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@ARTICLE{e101-c_4_197,
author={Tohru KANEKO, Yuya KIMURA, Masaya MIYAHARA, Akira MATSUZAWA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 72.4dB-SNDR 20MHz-Bandwidth Continuous-Time ΔΣ ADC with High-Linearity Gm-Cells},
year={2018},
volume={E101-C},
number={4},
pages={197-205},
abstract={A continuous-time (CT) ΔΣ analog-to-digital converter (ADC) is a high resolution, wide-bandwidth ADC. A Gm-C filter is suitable for low power consumption and its frequency characteristics for a loop filter of the ADC. However, in practice, distortion generated in the Gm-C filter degrades the SNDR of the ADC, therefore a high-linearity Gm-cell with low power consumption is needed. A flipped voltage follower (FVF) Gm-cell is also used as a high-linearity Gm-cell, but distortion is caused by variation of drain-source voltage of its input transistors. In this paper, a new high-linearity Gm-cell is proposed for the CT ΔΣ ADC in order to address this problem. A proposed topology is a combination of a FVF and a cascode topology. The inserted transistors in the proposed Gm-cell behave as cascode transistors, therefore the drain-source voltage variation of the input transistor and a PMOS transistor for current source which causes distortion is suppressed. Simulation results show the proposed Gm-cell can realize the same linearity as the conventional Gm-cell with reducing 36% power consumption. A 20MHz-bandwidth CT ΔΣ ADC employing the proposed Gm-cells achieves SNDR of 72.4dB with power consumption of 6.8mW. Active area and FoM of the ADC are, respectively, 250μm × 220μm and 50fJ/conv.-step in 65nm CMOS process.},
keywords={},
doi={10.1587/transele.E101.C.197},
ISSN={1745-1353},
month={April},}

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TY - JOUR
TI - A 72.4dB-SNDR 20MHz-Bandwidth Continuous-Time ΔΣ ADC with High-Linearity Gm-Cells
T2 - IEICE TRANSACTIONS on Electronics
SP - 197
EP - 205
AU - Tohru KANEKO
AU - Yuya KIMURA
AU - Masaya MIYAHARA
AU - Akira MATSUZAWA
PY - 2018
DO - 10.1587/transele.E101.C.197
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E101-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2018
AB - A continuous-time (CT) ΔΣ analog-to-digital converter (ADC) is a high resolution, wide-bandwidth ADC. A Gm-C filter is suitable for low power consumption and its frequency characteristics for a loop filter of the ADC. However, in practice, distortion generated in the Gm-C filter degrades the SNDR of the ADC, therefore a high-linearity Gm-cell with low power consumption is needed. A flipped voltage follower (FVF) Gm-cell is also used as a high-linearity Gm-cell, but distortion is caused by variation of drain-source voltage of its input transistors. In this paper, a new high-linearity Gm-cell is proposed for the CT ΔΣ ADC in order to address this problem. A proposed topology is a combination of a FVF and a cascode topology. The inserted transistors in the proposed Gm-cell behave as cascode transistors, therefore the drain-source voltage variation of the input transistor and a PMOS transistor for current source which causes distortion is suppressed. Simulation results show the proposed Gm-cell can realize the same linearity as the conventional Gm-cell with reducing 36% power consumption. A 20MHz-bandwidth CT ΔΣ ADC employing the proposed Gm-cells achieves SNDR of 72.4dB with power consumption of 6.8mW. Active area and FoM of the ADC are, respectively, 250μm × 220μm and 50fJ/conv.-step in 65nm CMOS process.
ER -