Forward converter is most suitable for low voltage and high current applications such as LEDs, battery chargers, EHV etc. The active clamp transformer reset technique offers many advantages over conventional single-ended reset techniques, including lower voltage stress on the main switch, the ability to switch at zero voltage and duty cycle operation above 50 percent. Several papers have compared the functional merits of the active clamp over the more extensively used RCD clamp, third winding and resonant reset techniques. This paper discusses about a center clamp technique with one common core reset circuit making it suitable for wide input voltage applications with extended duty cycle.

We introduce a Welch FFT segment size selection method for FFT-based wide band spectrum measurement in the context of smart spectrum access (SSA), in which statistical spectrum usage information of primary users (PUs), such as duty cycle (DC), will be exploited by secondary users (SUs). Energy detectors (EDs) based on Welch FFT can detect the presence of PU signals in a broadband environment efficiently, and DC can be estimated properly if a Welch FFT segment size is set suitably. There is a trade-off between detection performance and frequency resolution in terms of the Welch FFT segment size. The optimum segment size depends on signal-to-noise ratio (SNR) which makes practical and optimum segment size setting difficult. For this issue, we previously proposed a segment size selection method employing a relationship between noise floor (NF) estimation output and the segment size without SNR information. It can achieve accurate spectrum awareness at the expense of relatively high computational complexity since it employs exhaustive search to select a proper segment size. In this paper, we propose a segment size selection method that offers reasonable spectrum awareness performance with low computational complexity since limited search is used. Numerical evaluations show that the proposed method can match the spectrum awareness performance of the conventional method with 70% lower complexity or less.

This paper presents a mathematical model for the oscillator-based true random number generator (TRNG) to study the influence of some key parameters to the randomness of the output sequence. The output of the model is so close to the output of the real design of the TRNG that the model can generate the random bits instead of the analog simulation for research. It will cost less time than the analog simulation and be more convenient for the researchers to change some key parameters in the design. The authors give a method to improve the existing design of the oscillator-based TRNG to deal with the possible bias of the key parameters. The design is fabricated with a 55-nm CMOS process.

This paper discusses a pulse generator implemented by CMOS flipped on a glass substrate aiming at low power applications with low duty cycle. The pulse generator is theoretically possible to generate a pulse at a frequency near and beyond Fmax. It also features a quick starting time and zero stand-by power. By using a simplified circuit model, analytical expressions for Q factor, energy conversion efficiency, output energy, and oscillation frequency of the pulse generator are derived. Pulse generator prototypes are designed on a 0.18 μm CMOS chip flipped over a transmission line resonator on a glass substrate. Measurement results of two different prototypes confirm the feasibility of the proposed circuit and the analytical model.

We create a practical method to set the segment size of the Welch FFT for wideband and long-term spectrum usage measurements in the context of hierarchical dynamic spectrum access (DSA). An energy detector (ED) based on the Welch FFT can be used to detect the presence or absence of primary user (PU) signal and to estimate the duty cycle (DC). In signal detection with the Welch FFT, segment size is an important design parameter since it determines both the detection performance and the frequency resolution. Between these two metrics, there is a trade-off relationship which can be controlled by adjusting the segment size. To cope with this trade-off relationship, we define an optimum and, more easy to analyze sub-optimum segment size design criterion. An analysis of the sub-optimum segment size criterion reveals that the resulting segment size depends on the signal-to-noise ratio (SNR) and the DC. Since in practice both SNR and DC are unknown, proper segment setting is difficult. To overcome this problem, we propose an adaptive segment size selection (ASSS) method that uses noise floor estimation outputs. The proposed method does not require any prior knowledge on the SNR or the DC. Simulation results confirm that the proposed ASSS method matches the performance achieved with the optimum design criterion.

A 125MHz 64-phase delay-locked loop (DLL) is implemented for time recovery in a digital wire-line system. The architecture of the proposed DLL comprises a coarse-locking circuit added to a conventional DLL circuit, which consists of a delay line including a bias circuit, phase detector, charge pump, and loop filter. The proposed coarse-locking circuit reduces the locking time of the DLL and prevents harmonic locking, regardless of the duty cycle of the clock. In order to verify the performance of the proposed coarse-locking circuit, a 64-phase DLL with an operating frequency range of 40 to 200MHz is fabricated using a 0.18-µm 1-poly 6-metal CMOS process with a 1.8V supply. The measured rms and peak-to-peak jitter of the output clock are 3.07ps and 21.1ps, respectively. The DNL and INL of the 64-phase output clock are measured to be -0.338/+0.164 LSB and -0.464/+0.171 LSB, respectively, at an operating frequency of 125MHz. The area and power consumption of the implemented DLL are 0.3mm2 and 12.7mW, respectively.

This paper addresses a high-level synthesis (HLS) using dual-edge-triggered flip-flops (DETFFs) as memory elements. In DETFF-based HLS, the duty cycle becomes a manageable resource to improve the timing performance. To utilize the duty cycle radically, a programmable duty cycle (PDC) mechanism is built into this HLS, and captured by a new HLS task named PDC scheduling. As a first step toward DETFF-based HLS with PDC, the execution time minimization problem is formulated for given results of operation scheduling. A linear program is presented to solve this problem in polynomial time. As a next step, simultaneous operation scheduling and PDC scheduling problem for the same objective is tackled. A mixed integer linear programming-based (MILP) approach is presented to solve this problem. The experimental results show that the MILP can reduce the execution time for several benchmarks.

In this paper, an active control scheme is designed for the hybrid direct methanol fuel cell (DMFC) system to achieve the following three objectives simultaneously: (i) maximize the power produced by the DMFC stack in the stable operation as high loading (for avoiding the operation of DMFC in diffusion region), (ii) keep the power produced by the DMFC stack with the high efficiency as low loading, (iii) prevent the problem of methanol crossover at a very low load. Considering the characteristics of DMFC stack during actual operation, the states VP (t) and P (t) are utilized as the linguistic variables. Also considering the fuel efficiency of DMFC stack ηfuel as the linguistic variable, the active control scheme is designed to achieve the above multiple objectives. To clarify the reliability and stability of the proposed control scheme, an experiment is performed. Its results show that the proposed control scheme can achieve above multiple objectives efficiently.

This paper proposes a medium access control (MAC) mechanism for the recently developed IEEE 802.15.4 standard, a promising candidate to become the physical (PHY) and MAC layer standard for Wireless Sensor Networks (WSNs). The main concern in WSNs is the energy consumption, and this paper presents a mechanism that adapts properly the duty cycle operation according to the traffic conditions. Various traffic adaption mechanisms have been presented for the MAC layer of the IEEE 802.15.4. However these conventional mechanisms only consider the temporal traffic fluctuations. The proposed mechanism outperforms the conventional mechanism when applied to cluster-tree based WSNs, because it considers not only the temporal fluctuations but also the spatial (geographical) fluctuations, which are intrinsic characteristics of traffic in WSNs with the cluster tree topology. Evaluations showed that the proposed mechanism achieves less energy consumption than the conventional traffic adaptation mechanism, with maintaining almost the same transmission performance.

A proposed pseudo fractional-N clock generator with 50% duty cycle output is presented by using the pseudo fractional-N controller for SoC chips and the dynamic frequency scaling applications. The different clock frequencies can be generated with the particular phase combinations of a four-stage voltage-controlled oscillator (VCO). It has been fabricated in a 0.13 µm CMOS technology, and work with a supply voltage of 1.2 V. According to measured results, the frequency range of the proposed pseudo fractional-N clock generator is from 71.4 MHz to 1 GHz and the peak-to-peak jitter is less than 5% of the output period. Duty cycle error rates of the output clock frequencies are from 0.8% to 2% and the measured power dissipation of the pseudo fractional-N controller is 146 µW at 304 MHz.

A wide range, low jitter Duty Cycle Corrector (DCC) based on continuous-time integrator is proposed. It introduces little added jitter in the sampling edge, which make it good candidate for pipelined ADC application. The circuit is implemented in CMOS 0.35 µm 2P4M Mixed Signal process. The experimental results show the circuit can work for a wide frequency range from 500 kHz to 280 MHz, with a correction error within 50%1% under 200 MHz, and the acceptable duty cycle can be as wide as 1-99% for low frequency inputs.

To be adaptive to the bursty traffic of the wireless personal area network (WPAN), a superframe structure adjustment algorithm of IEEE 802.15.4 is proposed. According to the channel utilization ratio which is an index of the traffic load, the algorithm adjusts the duty cycle of the superframe automatically. The simulation results show that the algorithm is adaptive to the traffic variations effectively and saves much more energy not only for the end devices but also for the PAN coordinator. Moreover, the algorithm results in better performance on the lower delay and lower packet dropping rate.

This letter describes a digitally controlled duty cycle corrector (DCC) with 1 ps resolution. A new half period delay line (HPDL) control scheme using a delay locked loop (DLL) is proposed. The DCC has an output duty error less than 0.5% for 25% input duty error and operates correctly from 200 MHz to 800 MHz in a 0.18 µm CMOS technology.

An 8.8-GS/s 6-bit CMOS analog-to-digital converter (ADC) chip was implemented by time-interleaving eight 1.1-GS/s 6-bit flash ADCs with a 0.18-µm CMOS process. Eight uniformly-spaced 1.1 GHz clocks with 50% duty cycle for the eight flash ADCs were generated by a clock generator, which consists of a phase-locked-loop, digital phase adjusters and digital duty cycle correctors. The input bandwidth of ADC with the ENOB larger than 5.0 bits was measured to be 1.2 GHz. The chip area and power consumption were 2.24 mm2 and 1.6 W, respectively.

A second order charge pump (SOCP) scheme is proposed in this letter. Compared with the conventional single charge pump, the second order charge pump does not suffer phase errors caused by the output voltage dependent current mismatches. Also, the second order charge pump can be implemented in a mixed-mode type, enabling the fast lock and the various operation modes simultaneously. The proposed SOCP has been adopted into the duty cycle corrector (DCC) loops of DDR2 DRAM, and shows a much widened correction range owing to the removal of the parasitic effects.

An all-digital clock deskew buffer with variable duty cycles is presented. The proposed circuit aligns the input and output clocks with two cycles. A pulsewidth detector using the sequential time-to-digital conversion is employed to detect the duty cycle. The output clock with adjustable duty cycles can be generated. The proposed circuit has been fabricated in a 0.35 µm CMOS technology. The measured duty cycle of the output clock can be adjusted from 30% to 70% in steps of 10%. The operation frequency range is from 400 MHz to 600 MHz.

Four 50% duty-cycle divide-by-3 prescalers--positively/ negatively triggered sample-sample-hold (SSH) and sample-hold-hold (SHH) prescalers--are designed based on the current switchable D flip-flops and discussed in this paper. The positively triggered SSH and SHH prescalers are fabricated using the 0.35-µm SiGe BiCMOS technology and measured by the real-time oscilloscope and the spectrum analyzer. The SHH prescaler is our proposed structure and demonstrated in this paper. According to the measurement results, under the condition of the same input power, its maximum operation frequency is twice as high as that of the SSH prescaler thanks to better signal synchronization. At 2.7 V supply, the SSH prescaler operates from 500 MHz to 2 GHz as the SHH prescaler performs from 1 GHz to 3.4 GHz. The input sensitivity level of both structures is about -5 dBm, while the maximum output power is also about -5 dBm. The core current consumption is 4.538 mA and 4.258 mA for the SSH and SHH prescalers, respectively.

A false lock free delay-locked loop(DLL) achieving a wide frequency operation and a fine timing resolution is presented. A novel false lock detection technique is proposed to solve the trade-off between a wide frequency range and false locks. This technique enables a fine timing resolution even at a high frequency. In addition, the duty cycle of the input clock is not required to be 50%. This technique is applied to the DLLs in analog front-end LSIs of digital camera systems, with a range of 465 MHz (16) and a timing resolution of 9(40 stages).

A wide-range multiphase delay-locked loop (DLL) using mixed-mode voltage-controlled delay lines (VCDLs) is presented. An edge-triggered duty cycle corrector is introduced to generate output clocks with 50% duty cycle. This DLL using an analog 3-states phase-frequency detector (PFD) and the proposed digital PFD can achieve low jitter operation over a wide frequency range without harmonic locking problems. It has been fabricated in a standard 0.25-µm CMOS technology and occupies a core area of 1 mm2 including the on-chip regulator and loop filter. For reference clocks from 20 MHz to 550 MHz, all the measured rms and peak-to-peak jitters are below 10 ps and 78 ps, respectively.

An all-digital CMOS duty cycle correction (DCC) circuit with a fixed rising edge was proposed to achieve the wide correction ranges of input duty cycle and PVT variations, the low standby power and the fast recovery from the standby mode for use in multi-phase clock systems. SPICE simulations showed that this DCC adjusts the output duty cycle to 500.7% for the wide range of input duty cycle from 15% to 85% at the input frequency of 1 GHz, within the commercial range of PVT corners. The all-digital implementation and the use of a toggle flip flop at the input stage enabled the wide correction ranges of PVT variations and input duty cycle, respectively.