In many different bioelectronic applications silicon field-effect devices such as transistors or nanowires are used. Usually native or thermally grown silicon oxides serve as interfacing layer to the liquid. For an effective voltage to current conversion of the devices, the main demands for interface layers are low leakage current, low defect density, and high input capacitance. In this article we describe the fabrication and characterization of ultra-thin silicon oxide/high-κ material stacks for bioelectronics. A combination of ultra-thin silicon oxide and DyScO3 revealed the best results. This material stack is particularly interesting for future fabrication of field-effect devices for bioelectronic applications.

To reduce the gate leakage current of AlGaN/GaN HEMTs, we selected ITO/Ni/Au for Schottky electrodes and Schottky characteristics were compared with those of Ni/Au electrodes. ITO/Ni/Au and Ni/Au electrodes were deposited by vacuum evaporation and annealed at 350 in nitrogen atmosphere. From the I-V evaluation results of ITO/Ni/Au electrodes, forward and reverse leakage currents were reduced. Schottky characteristics of ITO/Ni/Au electrodes were also improved compared to these of Ni/Au electrodes. In addition, substantial decrease of leakage currents was confirmed after the annealing of HEMTs with ITO/Ni/Au electrodes. This may be explained that ITO/AlGaN interface state became lower by the annealing. By the temperature dependence of I-V curves, clear dependence was confirmed for the gates with ITO/Ni/Au electrodes. On the other hand, small dependence was observed for those with Ni/Au electrodes. From these results, tunnel leakage currents were dominant for the gates with Ni/Au electrode. Thermal emission current was dominant for the gates with ITO/Ni/Au electrode. The larger temperature dependence was caused that ITO/AlGaN interface states were smaller than those for Ni/Au electrode. It was suggested that suppressed AlGaN Schottky barrier thinning was caused by the surface defect donors, then tunneling leakage currents were decreased. We evaluated HEMT characteristics with ITO/Ni/Au electrode and Ni/Au electrode. Id max and Gm max were similar characteristics, but Vth with ITO/Ni/Au electrode was shifted +0.4 V than that with Ni/Au electrode due to the higher Schottky barrier. It was confirmed to have a good pinch-off currents and low gate leakage currents by ITO/Ni/Au electrodes.

The process mapping of the ALD process of HfO2 using HfCl4 and H2O is reported. A thickness uniformity better than 3% was achieved over a 300 mm-wafer at a deposition rate of 0.52 Å/cycle. Usually, H2O purge period is set less than 10 sec to obtain reasonable throughput; however, the amounts of residual impurities (Cl, H) found to be in the order of sub%, and these impurities are piled up near the HfO2/Si interface. In order to reduce the piled up impurities, we proposed a 2-step deposition in which purge period for initial 10-20 cycles was set to be 90 sec and that for remaining cycles was usual value of 7.5 sec. The leakage current is reduced to 1/10 by using this 2-step deposition.

High-temperature stability of copper (Cu) gate AlGaN/GaN high electron mobility transistors (HEMTs) was investigated. Samples were annealed at various temperatures to monitor the changes on device performances. Current-voltage performance such as drain-source current, transconductance, threshold voltage and gate leakage current has no obvious degradation up to annealing temperature of 500 and time of 5 minutes. Also up to this temperature, no copper diffusion was found at the Cu and AlGaN interface by secondary ion mass spectrometry determination. At annealing temperature of 700 and time of 5 minutes, device performance was found to have degraded. Gate voltage swing increased and threshold voltage shifted due to Cu diffusion into AlGaN. These results indicate that the Schottky contact and device performance of Cu-gate AlGaN/GaN HEMT is stable up to annealing temperature of 500. Cu is a promising candidate as gate metallization for high-performance power AlGaN/GaN HEMTs.

The density gradient (DG) model is tested for its ability to describe tunneling currents through thin insulating barriers. Simulations of single barriers (MOS diodes, MOSFETs) and double barriers (RTDs) show the limitations of the DG model. For comparison, direct tunneling currents are calculated with the Schrodinger-Bardeen method and used as benchmark. The negative differential resistance (NDR) observed in simulating tunneling currents with the DG model turns out to be an artifact related to large density differences in the semiconductor regions. Such spurious NDR occurs both for single and double barriers and vanishes, if all semiconductor regions are equally doped.

We have developed 100 nm node CMOS technology, consisting of a 65 nm gate length and a 1.6 nm gate oxide thickness. The major transistor design issue is how to maintain drive current at supply voltage of only 1.0 V, while suppressing standby leakage current to a practical level for system-on-a-chip applications. In order to obtain thinner electrical equivalent oxide thickness with well-suppressed gate leakage current, we have adopted radical nitridation and poly-SiGe. We have also utilized low-energy ion-implantation, low-temperature CVD, and spike RTA technology to overcome the short channel effect. With supply voltage of 1.0 V, our generic transistor shows the drive current of 520/196 µA/µm with the off current of 0.5 nA/µm. We also designed high-speed (Ioff=5 nA/µm), ultrahigh-speed (Ioff=30 nA/µm) transistors, and low-standby power (Ioff=5 pA/µm), all of which can be deployed on the same chip.