RF noise in quarter-micron nMOSFETs is analysed on the device level based on Shockley's impedance field method. The impact of different transport models and physical parameters is discussed in detail. Well-calibrated drift-diffusion and energy-balance models give very similar results for noise current spectral densities and noise figures. We show by numerical simulations with the general-purpose device simulator DESSIS_ISE that the hot-electron effect on RF noise is unimportant under normal operating conditions and that thermal substrate noise is dominant below 0.5 GHz. The contribution of energy-current fluctuations to the terminal noise is found to be negligible. Application of noise sources generated in bulk full-band Monte Carlo simulations changes the noise figures considerably, which underlines the importance of proper noise source models for far-from-equilibrium conditions.

The validity and capability of an iterative coupling scheme between single-particle frozen-field Monte Carlo simulations and nonlinear Poisson solutions for achieving self-consistency is investigated. For this purpose, a realistic 0.1 µm lightly-doped-drain (LDD) n-MOSFET with a maximum doping level of about 2.5 1020 cm-3 is simulated. It is found that taking the drift-diffusion (DD) or the hydrodynamic (HD) model as initial simulation leads to the same Monte Carlo result for the drain current. This shows that different electron densities taken either from a DD or a HD simulation in the bulk region, which is never visited by Monte Carlo electrons, have a negligible influence on the solution of the Poisson equation. For the device investigated about ten iterations are necessary to reach the stationary state after which gathering of cumulative averages can begin. Together with the absence of stability problems at high doping levels this makes the self-consistent single-particle approach (SPARTA) a robust and efficient method for the simulation of nanoscale MOSFETs where quasi-ballistic transport is crucial for the on-current.

The density gradient (DG) model is tested for its ability to describe tunneling currents through thin insulating barriers. Simulations of single barriers (MOS diodes, MOSFETs) and double barriers (RTDs) show the limitations of the DG model. For comparison, direct tunneling currents are calculated with the Schrodinger-Bardeen method and used as benchmark. The negative differential resistance (NDR) observed in simulating tunneling currents with the DG model turns out to be an artifact related to large density differences in the semiconductor regions. Such spurious NDR occurs both for single and double barriers and vanishes, if all semiconductor regions are equally doped.

TCAD is gaining acceptance in the heterostructure industry. This article discusses the specific challenges a device simulator must manage to be a useful tool in designing and optimizing modern heterostructure devices. Example simulation results are given for HEMTs and HBTs, illustrating the complex physical processes in heterostructure devices, such as nonlocal effects in carrier transport, lattice self-heating, hot-electron effects, traps, electron tunneling, and quantum transport.

We present calculations of the linear-response conductance of a SiGe based single-electron transistor (SET). The conductance and the discrete charging of the quantum dot are calculated by free-energy minimization. The free-energy calculation takes the discrete level-spectrum as well as complex many-body interactions into account. The tunneling rates for tunneling through the source and lead barrier are calculated using Bardeen's transfer Hamiltonian formalism. The tunneling matrix elements are calculated for transitions between the zero-dimensional states in the quantum dot and the lowest subband in the one-dimensional constriction. We compare the results for the conductance peaks with those from calculations with a constant tunneling rate where the shape of the peaks is only due to energetic arguments.

Tunneling generation becomes increasingly important in modern devices both as a source of leakage and for special applications. Mostly, the observed phenomena are attributed to band-to-band tunneling, although from early investigations of Esaki diodes it is well known that at lower field strengths trap-assisted tunneling is responsible for non-ideal IV-characteristics. In this paper we apply microscopic models of trap-assisted and band-to-band tunneling, which were derived from first-principle quantum-mechanical calculations, in a general multi-device simulator. Special simplified versions of the models were developed for the purpose of fast numerical computations. We investigate pn-junctions with different doping profiles to reveal the relative contribution of the two tunneling mechanisms. Simulated currents as function of voltage and temperature are presented for each individual process varying the basic physical parameters. It turns out that the slope of reverse IV-characteristics dominated by trap-assisted tunneling is similar to those which are determined by band-to-band tunneling, if the localized state of the recombination center is only weakly coupled to the lattice. In the model such a slope is produced by field-enhancement factors of the Shockley-Read-Hall lifetimes expressing the probability of tunneling into (or out of) excited states of the electron-phonon system. The temperature dependence of these field-enhancement factors compensates to a certain extent the expected strong temperature effect of the Shockley-Read-Hall process. The latter remains larger than the temperature variation of phonon-assisted band-to-band tunneling, but not as much as often stated. Consequently, the slope of the IV-characteristics and their temperature dependence are not the strong criteria to distinguish between trap-assisted and band-to-band tunneling. The origin of tunnel currents in silicon rather depends on the sum of physical conditions: junction gradient, nature and concentration of defects, temperature and voltage range.

We present several challenging gridding problems for multi-dimensional device and process simulation and discuss how new strategies might contribute to their solution. Formulating grid quality requirements for the standard Scharfetter-Gummel box method discretization in device simulation, we demonstrate how the offsetting techniques compares with quadtree grid generation methods and how they apply to modern device designs. Further we present a grid adaptation approach which respects the grid quality criteria and touch upon the main adaptation difficulties within device simulation. For the 3D moving boundary grids in process simulation we present a new algorithm.

We compare the numerical results for electron direct tunneling currents for single gate oxides, ON- and ONO-structures. We demonstrate that stacked dielectrics can keep the tunneling currents a few orders of magnitude lower than electrostatically equivalent single oxides. We also discuss the impact of gate material and of the modeling of electron transport in silicon.