A 150 GHz fundamental oscillator employing an inter-stage matching network based on a transmission line is presented in this letter. The proposed oscillator consists of a two-stage common-emitter amplifier loop, whose inter-stage connections are optimized to meet the oscillation condition. The oscillator is designed in a 130-nm SiGe BiCMOS process that offers fT and fMAX of 350 GHz and 450 GHz. According to simulation results, an output power of 3.17 dBm is achieved at 147.6 GHz with phase noise of -115 dBc/Hz at 10 MHz offset and figure-of-merit (FoM) of -180 dBc/Hz.

This paper presents high efficiency Class-E and compact Doherty power amplifiers (PAs) with novel harmonics termination for handset applications using a GaAs/InGaP heterojunction bipolar transistor (HBT) process. The novel harmonics termination circuit effectively reduces the insertion loss of the matching circuit, allowing a device with a compact size. The Doherty PA uses a lumped-element transformer which consists of metal-insulator-metal (MIM) capacitors on an IC substrate, a bonding-wire inductor and short micro-strip lines on a printed circuit board (PCB). The fabricated Class-E PA exhibits a power added efficiency (PAE) as high as 69.0% at 1.95GHz and as high as 67.6% at 2.535GHz. The fabricated Doherty PA exhibits an average output power of 25.5dBm and a PAE as high as 50.1% under a 10-MHz band width quadrature phase shift keying (QPSK) 6.16-dB peak-to-average-power-ratio (PAPR) LTE signal at 1.95GHz. The fabricated chip size is smaller than 1mm2. The input and output Doherty transformer areas are 0.5mm by 1.0mm and 0.7mm by 0.7mm, respectively.

We experimentally demonstrate transistor operation in a vertical p+-MoS2/n-HfS2 van der Waals (vdW) heterostructure configuration for the first time. The HfS2/MoS2 heterojunction transistor exhibits an ON/OFF ratio of 104 and a maximum drain current of 20 nA. These values are comparable with the corresponding reported values for vdW heterojunction TFETs. Moreover, we study the effect of atmospheric exposure on the subthreshold slope (SS) of the HfS2/MoS2 transistor. Unpassivated and passivated devices are compared in terms of their SS values and IDS-VGS hysteresis. While the unpassivated HfS2/MoS2 heterojunction transistor exhibits a minimum SS value of 2000 mV/dec, the same device passivated with a 20-nm-thick HfO2 film exhibits a significantly lower SS value of 700 mV/dec. HfO2 passivation protects the device from contamination caused by atmospheric moisture and oxygen and also reduces the effect of surface traps. We believe that our findings will contribute to the practical realization of HfS2-based vdW heterojunction TFETs.

This paper describes the design and measurements of two-gain-mode MMIC power amplifier modules (PAMs) for Band 1 and Band 5 WCDMA data communications. The PAMs are based on the two-stage single-chain amplifier topology with an L-shaped FET step attenuator (ATT) placed at the interstage, featuring not only high-efficiency operation but also both a small phase discontinuity and a small input return loss variation between the two gain modes: a high-gain mode (0-dB thru state for the ATT) and a low-gain mode (14-dB attenuation state for the ATT). The PAMs are assembled on a 3 mm × 3 mm FR-4 laminate together with several surface mount devices, and a high-directivity, 20-dB bilayer-type directional coupler is integrated on the laminate for accurate forward-power monitoring even under a 2.5:1-VSWR load mismatching condition. To validate the design and analysis for the PAMs using the L-shaped ATT, two PAM products — a Band 1 PAM and a Band 5 PAM — were fabricated using our in-house GaAs-BiFET process. The main RF measurements under the condition of a WCDMA (R99) modulated signal and a 3.4-V supply voltage are as follows. The Band 1 PAM can deliver a power-added efficiency (PAE) as high as 46% at an output power (Pout) of 28.25 dBm while maintaining a ±5-MHz-offset adjacent channel power ratio (ACLR1) of approximately -40 dBc or less and a small phase discontinuity of less than 5°. The Band 5 PAM can also deliver a high PAE of 46% at the same Pout and ACLR1 levels with small phase discontinuity of less than 4°. This small discontinuity is due to the phase-shift compensation capacitance embedded in the ATT. The measured input return loss is well maintained at better than 10 dB at the two modes. In addition, careful coupler design achieves a small detection error of less than 0.5 dB even under a 2.5:1-VSWR load mismatching condition.

This paper describes, for the first time, an experimental study on the layout design considerations of GaAs HBT MMIC switchable-amplifier-chain-based power amplifiers (SWPAs) for CDMA handsets. The transient response of the quiescent current and output power (Pout) in GaAs HBT power amplifiers that consist of a main chain and a sub-chain is often affected by a thermal coupling between power stages and their bias circuits in the same chain or a thermal coupling between power stages and/or their bias circuits in different chains. In particular, excessively strong thermal coupling inside the MMIC SWPA causes failure in 3GPP-compliant inner loop power control tests. An experimental study reveals that both the preheating in the main/sub-chains and appropriate thermal coupling inside the main chain are very effective in reducing the turn-on delay for the two-parallel-amplifier-chain topology; for example, i) the sub-power stage is arranged near the main power stage, ii) the sub-driver stage is placed near the main driver stage and iii) the main driver bias circuit is placed near the main power stage and the sub-power stage. The SWPA operating in Band 9 (1749.9 to 1784.9 MHz), which was designed and fabricated from the foregoing considerations, shows a remarkable improvement in the Pout turn-on delay: a reduced power level error of 0.74 dB from turn-off to turn-on in the sub-amplifier chain and a reduced power level error of over 0.30 dB from turn-off to turn-on in the main amplifier chain. The main RF power measurements conducted with a 3.4-V supply voltage and a Band 9 WCDMA HSDPA modulated signal are as follows. The SWPA delivers a Pout of 28.5 dBm, a power gain (Gp) of 28 dB, and a PAE of 39% while restricting the ACLR1 to less than -40 dBc in the main amplifier chain. In the sub-amplifier chain, 17 dBm of Pout, 23.5 dB of Gp, and 27% of PAE are obtained at the same ACLR1 level.

This paper describes, for the first time, the circuit design considerations and measurements of core building blocks that support a 1.9-GHz-band (Band I) BiFET MMIC three-power-mode power amplifier (PA) for WCDMA handset applications. The blocks are a reference voltage (Vref) generator, a control logic circuit, and ESD protection circuits. Our proposed Vref-generator, based on a current-mirror topology, can successfully suppress Vref variation against threshold voltage (Vth) dispersion in the FET as well as current gain dispersion in the HBT. On-wafer measurements over several wafer lots show that the standard deviation of Vref is as small as 18 mV over a Vth dispersion range from -0.6 V to -1.0 V. As a result, the measured quiescent current dispersion in the HPM is also suppressed to less than 5.4 mA, despite the fact that the average quiescent current is relatively high, at 81.3 mA. Several simulations reveal that small decoupling capacitances of approximately 1 pF added to the gate control lines of RF switch FETs ensure stable operation of the control logic even if an undesired RF coupling is present between an RF signal path and the gate lines. An empirical and useful design approach for ESD protection using HBT base-collector diodes allows easy and precise estimation of the HBM ESD robustness. With the above building blocks, a 3 mm × 3 mm PA was designed and fabricated by an in-house BiFET process. Measurements conducted under the conditions of a 3.4-V supply voltage and a 1.95-GHz WCDMA modulated signal are as follows. The PA delivers a 28.3-dBm output power (Pout), a 28.2-dB power gain (Gp), and 40% PAE while restricting the ACLR1 to less than -42 dBc in the HPM. In the MPM, 17.4 dBm of Pout, 15.9 dB of Gp, and 25.3% of PAE are obtained, while in the LPM, the PA delivers 7 dBm of Pout, 11.7 dB of Gp, and 13.9% of PAE. The HBM ESD robustness is 2 kV.

This paper investigates current-gain and high-frequency characteristics of double heterojunction bipolar transistors (DHBTs) with a uniform GaAsSb, compositionally graded GaAsSb, uniform InGaAsSb, or compositionally graded InGaAsSb base. DHBTs with a compositionally graded InGaAsSb base exhibit a high current gain of ∼75 and fT=504GHz. In order to boost fmax of DHBTs with a compositionally graded InGaAsSb base, a highly doped GaAsSb base contact layer is inserted. The fabricated DHBTs exhibit fT/fmax=513/637GHz and a breakdown voltage of 5.2V.

This paper describes the circuit design and measurement results of a new GaAs-HBT RF power detector proposed for use in WiMAX and wireless LAN transmitter applications. The detector, which is based on a simple current-mirror topology, occupies a small die area. It is, therefore, not only easy to implement together with a GaAs-HBT power amplifier, but can also offer approximately logarithmic (linear-in-dB) characteristics. Because it can also be driven with small voltage amplitudes, it is suitable for base-terminal monitoring at an HBT power stage. When the detector is used as a base-terminal power monitor, an appropriate base resistance added to the detection HBT effectively suppresses frequency dispersion of the detected voltage characteristics. Measurements of a prototype detector incorporated into a single-stage HBT power amplifier fabricated on the same die are as follows. The detector is capable of delivering a detected voltage of 0.35-2.5 V with a slope of less than 0.17 V/dB over a 4-to-24-dBm output power range at 3.5 GHz while drawing a current of less than 1.8 mA from a 2.85-V supply. While satisfying a log conformance error of less than 1 dB over an amplifier output power range from 4 dBm to 24 dBm, it can also suppress the detected power dispersion within 0.18 dB at approximately 15 dBm of output power over a 3.1-3.9-GHz-wide frequency range. This dispersion value is approximately one-tenth that of a conventional collector-terminal-monitor-type diode detector.

This paper describes 0.8-/1.5-GHz-band GaAs-HBT power amplifier modules with a newly designed analog bias control scheme. This scheme has two features. One is to achieve approximately linear quiescent current control using not a BiFET process but only the usual HBT process. The other is to help improve linearity under reduced supply voltage and lower quiescent current operation. The following two key techniques are incorporated into the bias scheme. The first is to employ two different kinds of bias circuits: emitter follower bias and current injection bias. The second is the unique current injection bias block, based on the successful combination of an input buffer with an emitter resistance load and a current mirror. These techniques allow quiescent current control that is almost proportional to an externally applied analog control voltage. To confirm the effectiveness of the scheme, 0.8-GHz-band and 1.5-GHz-band power amplifier modules were designed and fabricated using the usual HBT process. Measurements conducted under the conditions of a 3.4V supply voltage and an HSDPA WCDMA modulated signal are as follows. The 0.8-GHz-band amplifier can deliver a 28-dBm output power (Pout), a 28.4-dB power gain (Gp), and 42% PAE while restricting the ACLR to less than -40dBc. For the 1.5-GHz-band amplifier, 28dBm of Pout, 29dB of Gp, and 41% of PAE are obtained with the same ACLR levels. The measurements also confirm that the quiescent current for the second stage in the amplifiers is approximately linearly changed from 14mA to 58mA over a control voltage ranging from 1.1V to 2.2V. In addition, our measured DG.09-based current dissipation with both supply voltage and analog bias controls is as low as 16.9mA, showing that the analog bias control scheme enables an average current reduction of more than 20%, as compared to a conventional supply voltage and two-step quiescent current control.

This paper describes circuit design and measurement results of a newly proposed GaAs-HBT step-gain amplifier configuration and its application to a 3.3-3.6 GHz WiMAX power amplifier module for use in customer premises equipment. The step-gain amplifier implemented using only a usual HBT process is based on a current-mirror-based, base-collector diode switches and a passive attenuator core for the purpose of bypassing a power-gain stage. The stage allows an individual design approach in terms of gain and attenuation levels as well as large operating current reduction in the attenuation state. To confirm the effectiveness of the proposed step-gain amplifier, a prototype of the amplifier was designed and fabricated, and then a WiMAX power amplifier module was also designed and fabricated as an application example of the proposed configuration to an amplifier product. Measurements are as follows. For a 3.5-V power supply and a 3.5-GHz non-modulated signal, the step-gain amplifier delivers 23.7 dBm of 1-dB gain compressed output power and 10.7 dB of linear gain in the amplification state. In the attenuation state, the amplifier exhibits 21 dBm of 1-dB gain expanded input power, -9.7 dB of gain, and 15 mA of current dissipation while keeping the gain stage switched off and maintaining input and output return loss of less than -10 dB at a 3.5-GHz band. The WiMAX amplifier operating with a 5-V supply voltage and a 64-QAM modulated signal is capable of delivering a 28.5-dBm linear output power, a 37-39 dB gain, and 15% of PAE over a wide frequency range from 3.3 to 3.6 GHz in the high-gain state while keeping error vector magnitude as low as 2.5%. This amplifier, which incorporates the proposed step-gain configuration into its interstage, enables a 24-dB gain reduction and a 45-mA large quiescent current reduction in the low-gain state.

In this work, a gate-all-around (GAA) tunneling field-effect transistor (TFET) with InGaAs/Si heterojunction for high-performance and low-standby power operations is studied. Gallium (Ga) compositon ($x)$ in In$_{1-x}$Ga$_{x}$As source substantially affects the physical properties related with device performances including lattice constant, bandgap energy, effective tunneling mass, channel mobility, and others. Thus, it is worthy investigating the effect of Ga fraction on performances of the proposed heterojunction TFET. For this goal, the device design and its performance evaluation are carried out by technology computer-aided design (TCAD). Direct-current (DC) performances are investigated in terms of on-state current ($I_{ m{on}})$, off-state current ($I_{ m{off}})$, current ratio ($I_{ m{on}}$/$I_{ m{off}})$, and subthreshold swing ($S$). Furthermore, it is shown that the device with an n-type Si insertion layer between source and channel demonstrates the enhanced DC characteristics.

With the aim of achieving heterogeneous integration of compound semiconductors with silicon technology, the fabrication of an InP/InGaAs transferred-substrate HBT (TS-HBT) on a Si substrate is reported. A current gain of 70 and a maximum current density of 12.3 mA/µm2 were confirmed in a TS-HBT with a 340-nm-wide emitter. From microwave characteristics of the TS-HBT obtained after de-embedding, a cutoff frequency (fT) of 510 GHz and a 26% reduction of the base-collector capacitance were estimated. However, the observed fT was too high for an HBT with a 150-nm-thick collector. This discrepancy can be explained by the error in de-embedding, because an open pad is observed to have large capacitance and strong frequency dependence due to the conductivity of the Si substrate.

In this paper, we report the reduction in the base-collector capacitance (CBC) of InP/InGaAs double heterojunction bipolar transistors with buried SiO2 wires (BG-HBT). In a previous trial, we could not confirm a clear difference between the CBC of the conventional HBT and that of the BG-HBT because the subcollector layer was thicker than expected. In this study, the interface between the collector and the subcollector was shifted to the middle of the SiO2 wires by adjusting the growth temperature, and a reduction in CBC with buried SiO2 wires was confirmed. The estimated CBC of the BG-HBT was 7.6 fF, while that of the conventional HBT was 8.6 fF. This 12% reduction was in agreement with the 10% reduction calculated according to the designed size.

We have developed two modulator driver ICs that are based on the functional distributed circuit (FDC) topology for over 40-Gb/s optical transmission systems using InP HBT technology. The FDC topology enables both a wide bandwidth amplifier and high-speed digital functions. The none-return-to-zero (NRZ) driver IC, which is integrated with a D-type flip-flop, exhibits 2.6-Vp-p (differential output: 5.2 Vp-p) output-voltage swings with a high signal quality at 43 and 50 Gb/s. The return-to-zero (RZ) driver IC, which is integrated with a NRZ to RZ converter, produces 2.4-Vp-p (differential output: 4.8 Vp-p) output-voltage swings and excellent eye openings at 43 and 50 Gb/s. Furthermore, we conducted electro-optical modulation experiments using the developed modulator driver ICs and a dual drive LiNbO3 Mach-Zehnder modulator. We were able to obtain NRZ and RZ clear optical eye openings with low jitters and sufficient extinction ratios of more than 12 dB, at 43 and 50 Gb/s. These results indicate that the FDC has the potential to achieve a large output voltage and create high-speed functional ICs for over-40-Gb/s transmission systems.

Current density-voltage (J-V) and capacitance-voltage (C-V) characteristics of P3HT/n--silicon heterojunction diodes were investigated to clarify the carrier conduction mechanism at the organic/inorganic heterojunction. The J-V characteristics of the P3HT/n--Si junctions can be explained by a Schottky diode model with an interfacial layer. Diode parameters such as Schottky barrier height and ideality factor were estimated to be 0.78 eV and 3.2, respectively. The C-V analysis suggests that the depletion layer appears in the n--Si layer with a thickness of 1.2 µm from the junction with zero bias and the diffusion potential was estimated at 0.40 eV at the open-circuit condition. The present heterojunction allows a photovoltaic operation with power conversion efficiencies up to 0.38% with a simulated solar light exposure of 100 mW/cm2. The forward bias current was enhanced by coating the Si surface with a SiC layer, where the ideality factor was improved to be the level of 1.451.50.

In this paper, we report the fabrication and device characteristics of InP/InGaAs double heterojunction bipolar transistors (DHBTs) with buried SiO2 wires. The SiO2 wires were buried in the collector and subcollector layers by metalorganic chemical vapor deposition toward reduction of the base-collector capacitance under the base electrode. A current gain of 22 was obtained at an emitter current density of 1.25 MA/cm2 for a DHBT with an emitter width of 400 nm. The DC characteristics of DHBTs with buried SiO2 wires were the same as those of DHBTs without buried SiO2 wires on the same substrate. A current gain cutoff frequency (fT) of 213 GHz and a maximum oscillation frequency (fmax) of 100 GHz were obtained at an emitter current density of 725 kA/cm2.

A monolithic modulator driver IC based on InP HBTs with a new circuit topology -- called a functional distributed circuit (FDC) -- for over 80-Gb/s optical transmission systems has been developed. The FDC topology includes a wide-band amplifier designed using a distributed circuit, a digital function designed using a lumped circuit, and broadband impedance matching between the lumped circuit and distributed circuit to enable both wider bandwidth and digital functions. The driver IC integrated with a 2:1 multiplexing function produces 2.6-Vp-p (differential output: 5.2 Vp-p) and 2.4- Vp-p (differential output: 4.8 Vp-p) output-voltage swings with less than 450-fs and 530-fs rms jitter at 80 Gb/s and 90 Gb/s, respectively. To the best of our knowledge, this is equivalent to the highest data rate operation yet reported for monolithic modulator drivers. When it was mounted in a module, the driver IC successfully achieved electro-optical modulation using a dual-drive LiNbO3 Mach-Zehnder modulator up to 90 Gb/s. These results indicate that the FDC has the potential to realize high-speed and functional ICs for over-80-Gb/s transmission systems.

Indium-sulfide-oxide thin films have been successfully deposited on indium-tin-oxide-coated glass from an aqueous solution containing Na2S2O3 and In2(SO4)3 by electrochemical deposition using a periodic 2-step-pulse voltage. The films have been annealed in nitrogen atmosphere for an hour at different temperatures; namely, 100, 200, 300 and 400. Then, the as-deposited and annealed films were characterized structurally, morphologically and optically. X-ray photoelectron spectroscopy (XPS) study was performed in order to understand the chemical states of the oxygen involved in the film composition. The photosensitivity was observed by means of photoelectrochemical measurements, which confirmed that the as-deposited and annealed films showed n-type conduction. Moreover, a heterostructure solar cell that has indium sulfide as a buffer layer and tin sulfide as an absorber was fabricated and characterized.

Electrical characteristics of P3HT/Aluminum organic/ inorganic heterojunction diodes were investigated V-I and capacitance-voltage (C-V) measurements. The V-I measurement exhibited current rectification inherent in the Schottky diode, suggesting their availabilities as rectification diodes in organic flexible circuits. C-V analysis indicated the fact that the depletion layer was generated in the P3HT film in the reversed bias condition. The flat band voltage analysis suggested that the interfacial charge affected the built-in potential of the diodes. Al/P3HT heterojunction is possible to be used as not only the rectification diodes but also gate junctions for junction type field effect or static induction transistors.

The mechanism of current collapse of AlGaN/GaN heterojunction field-effect transistors (HFETs) was investigated by gate bias stress with and without illumination. It is clarified that there are two positions where negative charges accumulate, at the gate edge and in the bulk epi-layer. In the gate-edge mode, the charge comes either through the passivation film or the AlGaN layer, depending on the resistance of the films. Reduction of leakage current in the passivation film will be important to suppress the surface-related collapse.