In this paper, we propose a hybrid crystal oscillator which achieves both quick startup and low steady-state power consumption. At startup, a large negative resistance is realized by configuring a Pierce oscillating circuit with a multi-stage inverter amplifier, resulting in high-speed startup. During steady-state oscillation, the oscillator is reconfigured as a class-C complementary Colpitts circuit for low power consumption and low phase noise. Prototype chips were fabricated in 65nm CMOS process technology. With Pierce-type configuration, the measured startup time and startup energy of the oscillator are reduced to 1/11 and 1/5, respectively, compared with the one without Pierce-type configuration. The power consumption during steady oscillation is 30 µW.

This paper describes a broadband low phase noise VCO implemented in 0.13 µm CMOS process. A 1-bit switched varactor and a 4-bit capacitor array are adopted in cooperation with the automatic frequency calibration (AFC) circuit to lower the VCO tuning gain (KVCO), with a measured AFC time of 6 µs. Several noise reduction techniques are exploited to minimize the phase noise of the VCO. Measurement results show the VCO generates a high frequency range from 11.37 GHz to 14.8 GHz with a KVCO of less than 270 MHz/V. The prototype exhibits a phase noise of -114.6 dBc/Hz @ 1 MHz at 14.67 GHz carrier frequency and draws 10.5 mA current from a 1.2 V supply. The achieved figure-of-merits (FoM=-186.9dBc/Hz, FoMT=-195.3dBc/Hz) favorably compares with the state-of-the-art.

This paper describes a novel composite right-/left-handed (CRLH) transmission line (TL) stub resonator for X-band low phase-noise oscillator application. The bandpass filter type resonator composed only of microstrip components exhibits unloaded-Q exceeding that of microstrip-line resonators by engineering the dispersion relation for the CRLH TL. Two different types of stub resonator using identical and non-identical unit-cells are compared. Although the latter type was found to be superior to the former in terms of spurious frequency responses and the circuit size, care was taken to prevent the parasitic inductances distributed in the interdigital capacitors from impeding the Q-factor control capability of the resonator. The stub resonator thus optimized was applied to an 8.8-GHz SiGe HBT oscillator, which achieved a phase-noise of -134dBc/Hz at 1-MHz offset despite the modest dielectric loss tangent of the PCB laminate used as the substrate of the circuit.

This paper present a 20-GHz differential push-push voltage controlled oscillator (VCO) for 60-GHz frequency synthesizer. The 20-GHz VCO consists of a 10-GHz in-phase injection-coupled QVCO (IPIC-QVCO) with tail-filter and a differential output push-push doubler for 20-GHz output. The VCO fabricated in 65-nm CMOS technology, it achieves tuning range of 3 GHz from 17.5 GHz to 20.4 GHz with a phase noise of -113.8 dBc/Hz at 1 MHz offset. The core oscillator consumes up to 71 mW power and a FoM of -180.2 dBc/Hz is achieved.

This paper presents a constant-current-controlled class-C VCO using a self-adjusting replica bias circuit. The proposed class-C VCO is more suitable in real-life applications as it can maintain constant current which is more robust in phase noise performance over variation of gate bias of cross-coupled pair comparing to a traditional approach without amplitude modulation issue. The proposed VCO is implemented in 180,nm CMOS process. It achieves a tuning range of 4.8--4.9,GHz with a phase noise of -121,dBc/Hz at 1,MHz offset. The power consumption of the core oscillators is 4.8,mW and an FoM of -189,dBc/Hz is achieved.

This paper presents a 20 GHz push-push VCO realized by a 10 GHz super-harmonic coupled quadrature oscillator for a quadrature 60 GHz frequency synthesizer. The output nodes are peaked by a tunable second harmonic resonator. The proposed VCO is implemented in 65 nm CMOS process. It achieves a tuning range of 3.5 GHz from 16.1 GHz to 19.6 GHz with a phase noise of -106 dBc/Hz at 1 MHz offset. The power consumption of the core oscillators is 10.3 mW and an FoM of -181.3 dBc/Hz is achieved.

This paper presents a current-reused quadrature voltage-controlled oscillator (QVCO) which adopts a source-connection coupling structure. The QVCO simultaneously achieves low phase noise and low power consumption by newly combining current-reused VCOs and coupling transistors. The measured QVCO obtains good FoM of -188.2 dBc at a frequency of 2.2 GHz with 3.96 mW power consumption.

In this paper, a 24 GHz frequency source for low phase noise is presented in a 0.18 µm CMOS process. The 24 GHz frequency source chip is composed of a 12 GHz voltage controlled oscillator (VCO) and a 24 GHz balanced frequency doubler with class B gate bias. Compared to a conventional complementary VCO, the proposed 12 GHz VCO has phase noise improvement by using resistor current sources and substituting the nMOS cross-coupled pair in the conventional complementary VCO for a gm-boosted nMOS differential Colpitts pair. The measured phase noise and fundamental frequency suppression are -107.17 dBc/Hz at a 1 MHz offset frequency and -20.95 dB at 23.19 GHz frequency, respectively. The measured frequency tuning range is from 23.19 GHz to 24.76 GHz drawing 2.72 mA at a supply voltage of 1.8 V not including an output buffer.

This letter presents the design and analysis of phase noise optimization of a 4-GHz differential Colpitts voltage-controlled-oscillator (VCO). A low phase noise is achieved by a Colpitts oscillator and a VCO bias optimization using an amplitude control method. The measured phase noise is -134.8 dBc/Hz at 1.25 MHz offset frequency from 4 GHz operating frequency. The VCO is implemented using 0.24 µm SiGe BiCMOS process with integrated copper inductors. The wide VCO frequency range covers both PCS and IMT bands and draws about 15.9 mA from a 2.7 V power supply.

A VCO for multi-standard transceiver should operate in wide-tuning range, while providing low-phase noise quadrature outputs with low power consumption. In this paper, a multi-standard CMOS LC QVCO is designed utilizing reconfigurable LC tank and low power low phase noise quadrature generation method. Designed in 0.18 µm CMOS technology, the VCO achieved very wide tuning characteristics in two separate bands with low power consumption.

A simple low power low phase noise LC QVCO (Quadrature Voltage Controlled Oscillator) topology is proposed. The topology minimizes phase noise by eliminating the contributions from the tail current source and coupling transistors. With no more than 3.36 mW power consumption from a 1.2 V power supply, the VCO achieves -124 dBc/Hz phase noise performance at 1 MHz offset from the 2.85 GHz carrier frequency.

A fully integrated voltage controlled oscillator (VCO) MMIC for millimeter-wave applications has been designed and implemented in InGaP/GaAs heterojunction bipolar transistor (HBT) technology. To achieve a fully integrated VCO, a base-emitter diode is employed as the tuning varactor, and microstrip lines are employed for the transmission lines. The fabricated VCO MMIC chip size is 0.86 mm 1.34 mm and delivers an output power of 5.1 dBm at 28.7 GHz and a free-running phase noise of -118 dBc/Hz at 1 MHz offset. The dc current consumption is only 20 mA.

The low phase noise frequency source to be used for measurements and so on realizes by oscillator having highly output signal power against output noise power. SAW devices can be used with high power than BAW devices. So we examine on configuration of SAW oscillator circuits with the power gain. In this paper we shall discuss a configuration of oscillator circuit to obtain an extremely low phase noise and an oscillator operating at a non-reactive frequency of SAW resonator.