Design of an equivalent slew-rate monolithic pulse generator using bipolar-CMOS-DMOS (BCD) technology for medical ultrasound transmitters is presented in this paper. The pulse generator employs a floating capacitive coupling level-shifter architecture to produce a high-voltage (Vpp=80V) output. The performance of equivalent slew-rate in the rising and falling edge is achieved by carefully choosing the value of coupling capacitors and the size of the final stage high-voltage MOSFETs of the pulse generator. The measured output pulses show the rising and falling time of 8.6nsec and 8.5nsec, respectively with second harmonic distortion down to -40dBc, indicating the designed pulse generator can be used for advanced ultrasonic harmonic imaging systems.

A fully integrated CMOS pulse transceiver with digital beam-formability for mm-wave active imaging is presented. The on-chip pulse transmitter of the transceiver includes an eight-element antenna array connected to eight pulse transmitters and a built-in relative pulse delay calibration system. The receiver employs a non-coherent detection method by using a FET direct-power detection circuit integrated with an antenna. The receiver dipole-patch antenna derives from the transmitter antenna but is modified with an on-chip DC-bias tail by shorting two arms of the dipole. The bandwidth of the receiver antenna with the DC-bias tail is designed to achieve 50.4-GHz in simulation and to cover the bandwidth of transmitter antennas. The output of the receiver antenna is connected to a resistive self-mixer followed by an on-chip low pass filter and then an amplifier stage. The built-in relative pulse delay calibration system is used to align the pulse delays of each transmitter array elements for the purpose of controlling the beam steering towards imaging objects. Both transmitter and receiver chips are fabricated in a 65-nm CMOS technology process. Measured pulse waveform of the receiver after relatively aligning all Tx's pulses is 0.91 mV (peak-peak) and 3-ns duration with a distance of 25mm between Rx and Tx. Beam steering angles are achieved in measurement by changing the digital delay code of antenna elements. Experimental results show that the proposed on-chip transceiver has an ability of digital transmitted-pulse calibration, controlling of beam-steeting, and pulse detection for active imaging applications.

A 62ps timing resolution pulse generator (PG) is presented. The PG adopts the multi-phase ring oscillator and the pulse combiner circuit (PCC) to achieve the low timing error. The PCC can decide an arbitrary waveform via 16 phase outputs. PCC adopts the coarse-tuning stage (CTS) and the fine-tuning (FTS) to define the operational frequency range and the timing resolution, respectively. Hence, PCC uses edge combiner (EC) to combine the period window of CTS. The latency of PG is only 3 cycle times. The operational frequency range of PG is from 15MHz to 245MHz. The timing resolution and average accuracy of PG are 62.5ps and ±0.5 LSB, respectively. The RMS jitter and peak-to-peak jitter of PG are 6.55ps and 66.67ps, respectively, at 245MHz.

A readout technique using single-flux-quantum (SFQ) circuits enables superconducting single photon detectors (SSPDs) to operate at further high-speed, where a mutually-coupled dc-to-SFQ (MC-dc/SFQ) converter is used as an interface between SSPDs and SFQ circuits. In this work, we investigated pulse response of the MC-dc/SFQ converter. We employed on-chip pulse generators to evaluate pulse response of the MC-dc/SFQ converter for various pulses. The MC-dc/SFQ converter correctly operated for the pulse current with the amplitude of 52,$mu$A and the width of 179,ps. In addition, we examined influence of the pulse amplitude and width to operation of the MC-dc/SFQ converter by numerical simulation. The simulation results indicated that the MC-dc/SFQ converter had wide operation margins for pulse current with amplitudes of 30--60,$mu$A irrespective of the pulse widths.

A novel hybrid latch based flip-flop scheme is introduced in this paper. A pulse generator is eliminated to simplify clock distribution and save power. It also achieves high speed by shortening the critical data path. In addition, it avoids output node glitches which exist in conventional hybrid latch based flip-flops. HSPICE simulation results revealed that the proposed PHLFF performs best among referenced schemes. It can reduce 47.5% power dissipation, 16.5% clock-to-output latency and 56.4% PDP, as compared to conventional HLFF.

This paper presents the analytical results of the effects of jitter and intersymbol interference (ISI) on a millimeter-wave impulse radio (IR) transceiver, compared with the performance of a developed 10-Gb/s W-band IR-transmitter prototype. The IR transmitter, which is compact and cost-effective, consists of a pulse generator (PG) that creates an extremely short pulse, a band-pass filter (BPF) that shapes the short pulse to the desired millimeter-wave pulse (wavelet), and an optional power amplifier. The jitters of the PG and ISI from the BPF are a hindrance in making the IR transceiver robust and in obtaining excellent performance. One analysis verified that, because of a novel retiming architecture, the random jitter and the data-dependent jitter from the PG give only a small penalty of < 0.5-dB increase in the signal-to-noise ratio (SNR) for achieving a bit error rate (BER) of < 10-12. An alternative analysis on the effect of ISI from the BPF indicated that using a Gaussian BPF enables a transmission with a BER of < 10-12 up to a data rate of 1.4 times as large as the bandwidth of the BPF, which is twice as high as that of a conventional amplitude shift keying (ASK) system. The analysis also showed that the IR system is more sensitive to the ISI than the ASK system and suggested that the mismatching of the skirt characteristics of the developed BPF with those of a Gaussian BPF causes tail lobes following the wavelet, resulting in an on/off ratio of 15 dB and hence, an SNR penalty of 6 dB.

A low power pulse generator design using hybrid logic realization of a 3-input NAND gate is presented. The hybrid logic approach successfully shortens the critical path along the discharging transistor stack and thus reduces the short circuit power consumption during the pulse generation. The combination of pass transistor and full CMOS logic styles in one NAND gate design also helps minimize the required transistor size, which alleviates the loading capacitance of clock tree as well. Simulation results reveal that, compared with prior work, our design can achieve 20.5% and 23% savings respectively in power and circuit area.

Two novel low complexity dual-mode pulse generator designs suitable for FFs with triggering mode control are presented. The proposed designs successfully integrate XOR/OR (AND/XNOR) functions into a unified pass transistor logic (PTL) module to provide control on single- or double-edge operations. The designs use as few as 8 transistors each and ingeniously avoid the signal degradation problem inherent in most PTL circuits. As the only dual-mode designs so far, the proposed designs also outperform rival single-mode designs in both aspects of circuit complexity and power consumption.

Asynchronous optical packet switching (OPS) is a promising solution to support the continuous growth of transmission capacity demand. It has been, however, quite difficult to implement key functions needed at the node of such networks with all-optical approaches. We have proposed a new optoelectronic system composed of a packet-by-packet optical clock-pulse generator (OCG), an all-optical serial-to-parallel converter (SPC), a photonic parallel-to-serial converter (PSC), and CMOS circuitry. The system makes it possible to carry out various required functions such as buffering (random access memory), optical packet compression/decompression, and optical label swapping for high-speed asynchronous optical packets.

We describe the design of ECL write circuits and a CMOS memory cell in an ECL-CMOS SRAM to achieve ultra-fast cycle time. Factors determining the write cycle are reduced by several novel circuit techniques and by optimizing the design of the write circuits and CMOS memory cell, thereby, enabling ultra-fast cycle time. Key techniques are a bit line overdriving, the use of an overshoot suppressing emitter follower and a WPG with a replica memory cell delayer. The 72-kb ECL-CMOS SRAM macro through which these techniques were implemented was fabricated using 0. 3-µm BiCMOS technology. The RAM macro achieves a short cycle time of 2 ns without sacrificing stable memory cell operation. These techniques thus provide SRAMs with a shorter cycle time in the cache memories of high performance computer systems.

Feasibility of 20 Gbit/s single channel transoceanic soliton transmission systems with a simple EDFA repeaters configuration has been studied. Both a simple and versatile soliton pulse generator and a polarization insensitive optical demultiplexer, which can provide a almost square shape optical gate with duration of full bit time period, have been proposed and demonstrated by using sinusoidally modulated electroabsorption modulators. The optical time-division multiplexing/demultiplexing scheme using the optical demultiplexer results in drastic improvement of bit error rate characteristics. We have experimentally confirmed that the use of alternating-amplitude solitons is an efficient way to mitigate not only soliton-soliton interaction but also Gordon-Haus timing jitter constraints in multi-ten Gbit/s soliton transmission. Timing jitter reduction using relatively wide band optical filter bas been investigated in 20 Gbit/s loop experiments and single-carrier, single-polarization 20 Gbit/s soliton data transmission over 11500 km with bit error rate of below 10-9 has been experimentally demonstrated, using the modulator-based soliton source, the optical demultiplexer, the alternation-amplitude solitons, and wide-band optical filters. Obtained 230 Tbit/skm transmission capacity shows the feasibility of 20 Gbit/s single channel soliton transoceanic systems using fully practical technologies.

A 3.2 GHz, 50 mW, 1 V, GaAs clock pulse generator (CG) based on a phase-locked loop (PLL) circuit has been designed for use as an on-chip clock generator in future high speed processor LSIs. 0.5 µm GaAs MESFET and DCFL circuit technologies have been used for the CG, which consists of 224 MESFETs. An "enhanced charge-up current" inverter has been specially designed for a low power and high speed voltage controlled oscillator (VCO). In this new inverter, a voltage controlled dMESFET is combined in parallel with the load dMESFET of a conventional DCFL inverter. This voltage controlled dMESFET produces an additional charge-up current resulting in the new VCO obtaining a much higher oscillation frequency than that of a ring oscillator produced with a conventional inverter. With a single 1 V power supply (Vdd), SPICE calculation results showed that the VCO tuning range was 2.25 GHz to 3.65 GHz and that the average VCO gain was approximately 1.4 GHz/V in the range of a control voltage (Vc) from 0 to 1 V. Simulation also indicated that at a Vdd of 1 V the CG locked on a 50 MHz external clock and generated a 3.2 GHz internal clock (=50 MHz64). The jitter and power dissipation of the CG at 3.2 GHz oscillation and a Vdd of 1 V were less than 8.75 psec and 50 mW, respectively. The typical lock range was 2.90 GHz to 3.59 GHz which corresponded to a pull-in range of 45.3 MHz to 56.2 MHz.