In the past decade, real-time systems (RTSs), which must maintain time constraints to avoid catastrophic consequences, have been widely introduced into various embedded systems and Internet of Things (IoTs). The RTSs are required to be energy efficient as they are used in embedded devices in which battery life is important. In this study, we investigated the RTS energy efficiency by analyzing the ability of body bias (BB) in providing a satisfying tradeoff between performance and energy. We propose a practical and realistic model that includes the BB energy and timing overhead in addition to idle region analysis. This study was conducted using accurate parameters extracted from a real chip using silicon on thin box (SOTB) technology. By using the BB control based on the proposed model, about 34% energy reduction was achieved.

Silicon-on-insulator (SOI) has become one of the most famous materials in recent years, especially in silicon photonics applications. This paper presents a comparative performance of a SOI-based optical interconnect (OI) vs. an electrical interconnect (EI) for high-speed performances at a circuit level. The SOI-based optical waveguide was designed using OptiBPM to obtain a single mode condition (SMC). Then, the optical interconnect (OI) link was simulated in OptiSPICE and was tested as an interconnection in two-stage CS amplifiers. The results showed that the two-stage CS amplifier using OI offered several advantages in terms of electrical performances, such as voltage gain, frequency bandwidth, slew rate, and propagation delay, which makes it superior to the EI.

A multifunctional Boolean logic circuit composed of single-electron transistors (SETs) was fabricated and its operation demonstrated. The functions of Boolean logic can be changed by the half-period phase shift of the Coulomb-blockade (CB) oscillation of some SETs in the circuit, and an automatic control based on a feedback process is used to attain an exact shift. The amount of charges in the memory node (MN), which is capacitively coupled to the SET, controls the phase of the CB oscillation, and the output signal of the SET controls the amount of charge in the MN during the feedback process. This feedback process automatically adjusts SET output characteristics in such a way that it is used for the multifunctional Boolean logic. We experimentally demonstrated the automatic phase control and examined the speed of the feedback process by SPICE circuit simulation combined with a compact analytical SET model. The simulation revealed that programming time could be of the order of a few ten nanoseconds, thereby promising high-speed switching of the functions of the multifunctional Boolean logic circuit.

A silicon (Si) wire waveguiding system fabricated on silicon-on-insulator (SOI) substrates is one of the most promising platforms for highly-integrated, ultra-small optical circuits, or microphotonics devices. The cross-section of the waveguide's core is about 300-nm-square, and the minimum bending radius are a few micrometers. Recently, crucial problems involving propagation losses and in coupling with external circuits have been resolved. Functional devices using silicon wire waveguides are now being tested. In this paper, we describe our recent progress and future prospects on the microphotonics devices based on the silicon-wire waveguiding system.

The performance of radio frequency integrated circuits (RFICs) in silicon-on-insulator (SOI) technology can be improved by using a high-resistivity SOI substrate. We investigated the correlation between substrate resistivity and the performance of a low noise amplifier (LNA) on ELTRAN(R) SOI-Epi wafersTM, whose resistivity can be controlled precisely. The use of high-resistivity ELTRAN wafers improves the Q-factor of spiral inductors, and thereby increases the gain and narrows the bandwidth of the LNA. Using the high-resistivity ELTRAN wafers, we have successfully fabricated a 2.4-GHz and 5-GHz CMOS LNA in 0.35-µm SOI CMOS technology, whose process cost is lower than the latest CMOS technologies.

New physical models, algorithms, and parameters are needed to accurately model emerging silicon-on-insulator (SOI) devices. The modeling approaches for various emerging SOI technologies are discussed in this paper.

The radio-frequency thermal noise in fully-depleted (FD) silicon-on-insulator (SOI) MOSFETs and bulk MOSFETs is theoretically examined using a distributed-transmission-line model. It is shown that the thermal noise in a scaled-down SOI MOSFET is basically smaller than that in a scaled-down bulk MOSFET in a wide frequency range. In the radio-frequency range, parasitic resistances in source and drain don't yield a remarkable contribution to the difference in output thermal noise power between scaled-down bulk MOSFETs and scaled-down SOI MOSFETs. However, the output thermal noise of scaled-down SOI MOSFETs with a finite parasitic resistance is smaller than that of scaled-down bulk MOSFETs because of smaller channel capacitance.