This paper presents a new model which computes the deformation and the feedback force of high-resolution biomedical volumetric objects consisting of hundreds of thousands of volume elements. The main difficulty in the simulation of these high-resolution volumetric objects is to compute and generate stable feedback force from the objects within a haptic update time (1 msec). In our model, springs are used in order to represent material properties of volume elements and cylinders are used to activate corresponding springs according to the amount of deformation. Unlike in a mass-spring model, springs in our model have constraint conditions. In our model, the deformation is calculated locally and then is propagated outward through object's volume as if a chain is pulled or pushed. The deformed configuration is then used to compute the object's internal potential energy that is reflected to the user. The simple nature of our model allows the much faster calculation of the deformation and the feedback force from the volumetric deformable object than the conventional model (an FEM or a mass-spring model). Experiments are conducted with homogenous and non-homogenous volumetric cubic objects and a volumetric human liver model obtained from CT data at a haptic update rate of 1000 Hz and a graphic update rate of 100 Hz to show that our model can be utilized in the real-time volume haptic rendering. We verify that our model provides a realistic haptic feeling for the user in real time through comparative study.

This paper proposes a new framework to produce humanoid animations for simulating human tasks. Natural working movements are generated via management of motion capture data with our simulation package. An extensible middleware controls reactive human behaviors, and all processes of simulation in a cyber factory are controlled through XML documents including motions, scene objects, and behaviors. This package displays simulation using Web3D technology and X3D specifications which can supply a common interface for customizing cyberworlds.

We analyzed passivation film and the AlGaN surface states using open-gated structures of AlGaN/GaN HFETs by numerical simulation and experiments. From the analyses, we confirmed that insulating film conductivity plays the prominent roles in device performances of the wide bandgap semiconductor device. Device simulation confirmed that the difference in ID-VG characteristics is due to the trapping type of the surface states; electron-trap type or hole-trap type. For electron-trap type surface states, the surface potential pinned at electron quasi-Fermi level, which is the same as the channel potential in the open-gated FETs. As a result, surface potential of ungated region is equal to the channel electric potential resulting in the uncontrollability of the channel current by the edge placed gate electrode. For hole-trap type surface states, the surface potential is pinned at hole quasi-Fermi level, which must be the same as the edge placed gate electrode potential. Then, the AlGaN surface potential varies with the electrode potential variation allowing the control of channel current as if the whole channel is covered with a metal electrode. Experiments for open-gated FET with unpassivated surface show no current variation. This corresponds to electron-trap type surface states from the simulation. On the other hand, SiOX evaporated open-gated FET show current control by the gate electrode. The ID-VG characteristics resembles in simulated ID-VG characteristics with hole-trap surface states. However, the estimated time constants for the trap reactions are incredibly long due to the deep energy level for the surface states in wide bandgap semiconductors. In addition, the open-gated FET showed reverse threshold shift to the value expected from the hole-trap pinning levels. So, we concluded that the no current variation for the unpassivated open-gated FET can be attributed to electron traps in the surface states, but the control of the drain current for SiOX deposited open-gated FET is not by surface hole-traps, but by slightly conductive passivation film of SiOX.

In this paper, we present Scalable Data Collection (SDC) protocol, a tree-based protocol for collecting data over multi-hop, wireless sensor networks. The design of the protocol aims to satisfy the requirements of sensor networks that every sensor transmits sensed data to a sink node periodically or spontaneously. The sink nodes construct the tree by broadcasting a HELLO packet to discover the child nodes. The sensor receiving this packet decides an appropriate parent to which it will attach, it then broadcasts the HELLO packet to discover its child nodes. Based on this process, the tree is quickly created without flooding of any routing packets. SDC avoids periodic updating of routing information but the tree will be reconstructed upon node failures or adding of new nodes. The states required on each sensor are constant and independent of network size, thereby SDC scales better than the existing protocols. Moreover, each sensor can make forwarding decisions regardless of the knowledge on geographical information. We evaluate the performance of SDC by using the ns-2 simulator and comparing with Directed Diffusion, DSR, AODV, and OLSR. The simulation results demonstrate that SDC achieves much higher delivery ratio and lower delay as well as scalability in various scenarios.

Current literature on input buffer management reveals that, in representative ATM networks under highly bursty traffic conditions, the fuzzy thresholding approach yields lower cell loss rate at the cost of lower throughput. Also, under less bursty traffic, the traditional fixed thresholding approach achieves higher throughput at the expense of higher cell loss rate. The integration of these two properties into practice is termed adaptive dynamic buffer management (ADBM) approach for input buffers and its assessment is the objective of this paper. The argument is that, given that the traffic conditions are constantly changing, to achieve efficiency during actual operation, the network control must dynamically switch, at every ATM switch, under the call processor's control, between the two input buffer management techniques, dictated by the nature of the traffic at the inputs of the corresponding switch. The need to involve the call processor marks the first effort in the literature to dynamically configure input buffer management architectures at the switch fabric level under higher level call processor control. It stems from the fact that the switch fabric operates very fast and cannot engage in complex decision making without incurring stiff penalty. To achieve this goal, the network control needs knowledge of the burstiness of the traffic at the inputs of every ATM switch. The difficulties with this need are two-fold. First, it is not always easy to obtain the traffic model and model parameters for a specific user's call. Second, even where the traffic model and the model parameters are known for a specific user's call, this knowledge is valid only at the source switch where the user interfaces with the network. At all other switches in the network, the cells of the traffic in question interact asynchronously with the cells from other traffic sources and are subject to statistical multiplexing. Thus, to obtain the exact nature of the composite traffic at the inputs of any ATM switch, is a challenge. Conceivably, one may determine the burstiness by counting the number of cells incurred at the inputs of an ATM switch over a defined time interval. The challenge posed by this proposition lies in the very definition of burstiness in that the time interval must approach, in the limit, zero or the resolution of time in the network. To address this challenge, first, a 15-node representative ATM network is modeled in an asynchronous, distributed simulator and, second, simulated on a network of workstations under realistic traffic stimuli. Third, burstiness indices are measured for the synthetic, stochastic traffic at the inputs of every ATM switch as a function of the progress of simulation for different choices of time interval values, ranging from 20,000 timesteps down to 1,000 timesteps. A timestep equals 2.73 µs. Results reveal that consistent burstiness indices are obtained for interval choices between 1,000 and 5,000 timesteps and that a burstiness index of 25, measured at 3,000 timestep interval, constitutes a reasonable and practical threshold value that distinguishes highly bursty traffic that warrants the use of the fuzzy thresholding approach from less bursty traffic that can benefit from the fixed thresholding scheme. A comparative performance analysis of ADBM yields the following. For pure fixed and pure fuzzy thresholding schemes, the throughputs are at 73.88% and 71.53% while the cell drop rates are at 4.31% and 2.44%,respectively. For the ADBM approach, where the input buffer management alternates at each individual ATM switch between the fixed and fuzzy schemes, governed by measured burstiness index threshold of 25 for a 3,000 timestep interval, the throughput is 74.77%, which is higher than even the pure fixed scheme while the cell drop rate is 2.21% that is lower than that of the pure fuzzy scheme. In essence, ADBM successfully integrates the best characteristics of the fuzzy and fixed thresholding schemes.

The paper first researches the properties of neural networks in the framework of the dual linear programming theory, then discusses the variation range of a Hessian matrix associated to dual linear programming problems. By means of eigenvalues method, a Lipschitz constant based formula for determining the algorithm step-size is presented. Two examples are given to show that the proposed formula is efficacious.

Integrated 900-MHz ISM band transceiver LSI for analog cordless telephone has been realized by cost-effective process technology with sufficient performance. This LSI consisted of fully integrated transceiver, from RF-LNA to audio amplifier for RX chain, from microphone's amplifier to RF-PA for TX chain, and integrated RX- and TX-LO consisting of PLLs and VCOs. In view of narrow signal bandwidth with analog modulation, extremely low phase noise at low offset frequency from carrier was required for integrated VCO. Also, in view of fully duplex operations, signal isolation between TX and RX was required. Despite such a high integration and high performance, chip cost had to be minimized for low-cost applications. The 12-dB SINAD RX sensitivity was -111.2 dBm, the output power of TX was +3 dBm, and the phase noise of integrated VCO was -77 dBc/Hz at 3 kHz offset away from carrier. The current consumption at fully duplex operation was 76 mA at 3.6 V power supply. The chip was realized by 0.8 µm standard silicon BiCMOS process.

The comparative analysis of the well known Double Drift Region (DDR) IMPATT diode structure and the n+pvnp+ structure for the avalanche diode has been realized on the basis of the drift-diffusion nonlinear model. The last type of the diode was named as Double Avalanche Region (DAR) IMPATT diode. This structure includes two avalanche regions inside the diode. The phase delay which was produced by means of the two avalanche zones and the drift zone v is sufficient for the negative resistance obtained for the wide frequency region. The numerical model that is used for the analysis of the various diode structures includes all principal features of the physical phenomena inside the semiconductor structure. The admittance characteristics of both types of the diodes were analyzed in very wide frequency region.

This paper presents an efficient scaling-simulation algorithm that simulates operations of the reconfigurable mesh (RM) of size n n using the mesh with multiple partitioned buses (MMPB) of size m m (m < n). The RM and the MMPB are the two-dimensional mesh-connected computers equipped with broadcasting buses. The broadcasting buses of the RM can be used to dynamically obtain various interconnection patterns among the processors during the execution of programs, while those of the MMPB are placed only to every row and column and are statically partitioned in advance by a fixed length. We show that the RM of size n n can be simulated in steps by the MMPB of size m m (m < n), where L is the number of broadcasting buses in each row/column of the simulating MMPB. Although the time-complexity of our algorithm is less efficient than that of the fastest RM scaling-simulation algorithm, the simulating model of our algorithm is the MMPB model where the bus-reconfiguration is not allowed.

With the growing design complexity of contemporary embedded systems, real-time operating systems (RTOSs) have become one of important components of such complex embedded systems. This paper presents an RTOS-centric hardware/software cosimulator which we have developed for embedded system design. One of the most remarkable features in our cosimulator is that it has a complete simulation model of an RTOS which is widely used in industry, so that application tasks including RTOS service calls are natively executed on a host computer. Our cosimulator also features cosimulation with functional simulation models of hardware written in C/C++ and cosimulation with HDL simulators. A case study with a JPEG decoder application demonstrates the effectiveness of our cosimulator.

This paper proposes a new simulation algorithm for analyzing large power distribution networks, modeled as linear RLC circuits, based on a novel partial random walk concept. The random walk simulation method has been shown to be an efficient way to solve for voltages of small number of nodes in a large power distribution network, but the algorithm becomes expensive to solve for voltages of nodes that are more than a few with high accuracy. In this paper, we combine direct methods like LU factorization with the random walk concept to solve power distribution networks when voltage waveforms from a large number of nodes are required. We extend the random walk algorithm to deal with general RLC networks and show that Norton companion models for capacitors and self-inductors are more amenable for transient analysis by using random walks than Thevenin companion models. We also show that by nodal analysis (NA) formulation for all the voltage sources, LU-based direct simulations of subcircuits can be speeded up. Experimental results demonstrate that the resulting algorithm, called partial random walk (PRW), has significant advantages over the existing random walk method especially when the VDD/GND nodes are sparse and accuracy requirement is high.

Through many researches on modeling and analyzing biological pathways, Petri net has recognized as a promising method for representing biological pathways. Recently, Matsuno et al. (2003) introduced hybrid functional Petri net (HFPN) for giving more intuitive and natural biological pathway modeling method than existing Petri nets. They also developed Genomic Object Net (GON) which employs the HFPN as a basic architecture. Many kinds of biological pathways have been modeled with the HFPN and simulated by the GON. This paper gives a new HFPN model of "cell cycle of fission yeast" with giving six basic HFPN components of typical biological reactions, and demonstrating the method how biological pathways can be modeled with these HFPN components. Simulation results by GON suggest a new hypothesis which will help biologist for performing further experiments.

One of the important techniques in communication system design is the composition of service and protocol specifications. In this paper, we have presented a new approach to the composition technique based on the weak bisimulation concept. The main objective is to combine service specifications and protocol specifications individually and simultaneously. The composition technique can maintain the equivalence between the composed service and protocol specifications. LOTOS language terms are utilized to describe the communication specifications. The application on the asynchronous model is presented. Moreover, a support system of the composition technique is developed and presented in this paper.

Parallel concatenated convolutional codes, turbo codes, are very attractive scheme at a point of view of an error probability performance. An bit error rate (BER) evaluation for turbo codes is done by a uniform interleaver bound calculation and/or a computer simulation. The former is calculated under the assumption of uniform interleaver, and is only effective for an BER evaluation with a pseudo random interleaver. The latter dose not have any interleaver restrictions. However, for a very low BER evaluation, it takes enormous simulation time. In this paper, a new error probability evaluation method for turbo codes is proposed. It is based on the error event simulation method. For each evaluation for the predetermined error sequence, importance sampling, which is one of the fast simulation methods, is applied. To prove the effectiveness of the proposed method, numerical examples are shown. The proposed method well approximates the BER at the error floor region. Under the same accuracy, the IS estimation time at BER = 10-7 is reduced to 1/6358 of the ordinary Monte-Carlo simulation time.

We investigate the effects of DoS (Denial of Service) attacks in wireless ad hoc networks using simulations, concentrating on the problem of energy availability. Our results show that the damages due to the DoS attack may quite different with those in wired networks: First, the nodes along the transmission route mostly suffer damages rather than the victim node itself. Second, if the mobile nodes are crowded and close together, the damage becomes more severe. Lastly, if the nodes have random mobility, the attacker itself consumes more energy.

Since a radio channel is shared among terminals in an ad hoc network, packet collisions are frequent. In case of transmitting packets especially using TCP, data and ACK packets are transmitted in opposite directions on the same radio channel. Therefore, frequent collisions are unavoidable, and this seriously degrades TCP throughput. It is possible to transmit to two or more nodes which adjoin from a certain node simultaneously on the radio channel. To reduce the likelihood of packet collisions when an intermediate node transmits both data and ACK packets, these two types of packet can be combined and transmitted at the same time to increase the efficiency of radio channel utilization. In this paper, we propose a new technique to improve TCP performance by combining data and ACK packets. Our proposed technique is applicable to generic ad hoc networks easily. By means of a simulation using networks with various topologies, we have found that throughput can be improved by up to 60% by applying our proposed technique.

In this paper, we propose a new method which makes transient simulation faster for the circuit including both nonlinear and linear elements. First, the method for generating the projection matrix with Krylov-subspace technique is described. The order of the circuit equation is reduced by congruence transformation with the projection matrix. Next, we suggest a method which can calculate the reduced Jacobian matrix directly in each Newton-Raphson iteration. Since this technique does not need to calculate the original size of Jacobian matrix, the calculation cost is reduced drastically. Therefore, efficient circuit simulation can be achieved. Finally, our method is applied to some example circuits and the validity of the nonlinear circuit reduction technique is verified.

This paper presents a path compression protocol for on-demand ad hoc network routing protocols, which is called dynamic path shortening (DPS). In DPS, active route paths adapt dynamically to node mobility based on the "local" link quality estimation at each own node, without exchanging periodic control packets such as Hello messages. Each node monitors its own local link quality only when receiving packets and estimates whether to enter the "proximity" of the neighbor node to shorten active paths in a distributed manner. Simulation results of DPS in several scenarios of various node mobility and traffic flows reveal that adding DPS to DSR which is the conventional prominent on-demand ad hoc routing protocol significantly reduces the end-to-end packet latency up to 50-percent and also the number of routing packets up to 70-percent over the pure DSR, in heavy traffic cases. We also demonstrate the other simulation results obtained by using our two novel mobility models which generate more realistic node mobility than the standard random waypoint mobility model: Random Orientation Mobility and Random Escape Mobility models. Finally, simple performance experiments using DPS implementation on FreeBSD OS demonstrate that DPS shortens active routes in the order of milliseconds (about 5 ms).

This paper proposes a PCB plane model for generic circuit simulators (SPICE). The proposed model reflects two frequency-dependent losses, namely, skin and dielectric losses. Once power/ground plane pair is divided into arrays of unit-cells, each unit-cell is modeled using a transmission line and the loss model. The loss model is composed of a resistor for DC loss, series RL ladder circuit for skin loss and series RC ladder circuit for dielectric loss. To verify the validity of the proposed model, it is compared with SPICE ac analysis using frequency-dependent resistors. Also, we show that the estimation results using the proposed model have a good correlation with that of VNA measurement for the typical PCB stack-up structure of general desktop PCs. With the proposed model, not only ac analysis but also transient analysis can be easily done for circuits including various non-linear/linear devices since the model consists of passive elements only.

Computer simulation of cellular process is one of the most important applications in bioinformatics. Since such simulators need huge computational resources, many biologists must use expensive PC/WS clusters. ReCSiP is an FPGA-based, reconfigurable accelerator which aims to realize economical high-performance simulation environment on desktop computers. It can exploit fine-grain parallelism in the target applications by small hardware modules in the FPGA which work in parallel manner. As the first step to implement a simulator of cellular process on ReCSiP, a solver to perform a basic simulation of metabolism was implemented. The throughput of the solver was about 29 times faster than the software on Intel's PentiumIII operating at 1.13 GHz.