In this paper, a novel trench MOS barrier Schottky contact super barrier rectifier (TMB-SSBR) is proposed by combining the advantages of vertical SSBR and conventional TMBS. The operation mechanism and simulation verification are presented. TMB-SSBR consists of MOS trenches with a vertical SSBR grid which replaces the Schottky diode in the mesa of a TMBS. Due to the presence of top p-n junction in the proposed TMB-SSBR, the image force barrier lowering effect is eliminated, the pinching off electric field effect by MOS trenches is weakened, so that the mesa surface electric field is much larger than that in conventional TMBS. Therefore, the mesa width is enlarged and the n-drift concentration is slightly increased, which results in a low specific on-resistance and a good tradeoff between reverse leakage currents and forward voltages. Compared to a conventional TMBS, simulation results show that, with the same breakdown voltage of 124V and the same reverse leakage current at room temperature, TMB-SSBR increases the figure of merit (FOM, equates to VB2/Ron, sp) by 25.5%, and decreases the reverse leakage by 33.3% at the temperature of 423K. Just like the development from SBD to TMBS, from TMBS to TMB-SSBR also brings obvious improvement of performance.

The trench-gate type high-voltage (HV) MOSFET is one of the variants of HV-MOSFET, typically with its utility segments lying on a larger power consumption domain, compared to planar HV-MOSFETs. In this work, the HiSIM_HV compact model, originally intended for planar LDMOSFETs, was adequately extended to accommodate trench-gate type HV-MOSFETs. The model formulation focuses on a closed-form description of the current path in the highly resistive drift region, specific to the trench-gate HV-MOSFETs. It is verified that the developed compact expression can capture the conductivity in the drift region, which varies with voltage bias and device technology such as trench width. The notable enhancement of current drivability can be accounted for by the electrostatic control exerted by the trench gate within the framework of this model.

The dispersion and the splice characteristics of optical fibers with trench-index profile are investigated. The normalized distance between core and trench is preferably larger than 3.0 to realize complete compatibility with the standard G.652 fiber in terms of chromatic dispersion. The optical fiber realizes compatibility with ITU-T Recommendation G.652 fiber and bend-insensitivity simultaneously. Fabricated fibers with the trench-index profiles can be spliced to standard single-mode fiber with low losses, which have similar values with simulation results.

A compact arrayed-waveguide grating with small-bend waveguides incorporating air trenches and high mesa structures has been proposed. An 8-channel, 100-GHz-spacing silica arrayed-waveguide grating was fabricated, and its size was reduced dramatically to 1/4 of that of a conventional device.

An efficient adaptation technique of the delay is introduced for accomplishing more accurate adaptive linear equalization of nonminimum phase channels. It is focused that the filter structure and adaptation procedure of the adaptive Butler-Cantoni (ABC) equalizer is very suitable to deal with a variable delay for each iteration, compared with a classical adaptive linear transversal equalizer (LTE). We derive a cost function by comparing the system mismatch of an optimum equalizer coefficient vector with an equalizer coefficient vector with several delay settings. The cost function is square of difference of absolute values of the first element and the last element for the equalizer coefficient vector. The delay adaptation method based on the cost function is developed, which is involved with the ABC equalizer. The delay is adapted by checking the first and last elements of the equalizer coefficient vector and this results in an LTE providing a lower mean square error level than the other LTEs with the same order. We confirm the performance of the ABC equalizer with the delay adaptation method through computer simulations.

A single-mode fiber employing a trench index profile for indoor wiring is proposed to realize low-bending loss and low-splice loss simultaneously. The designs and the advantages of the fiber over fibers with conventional step index profiles are described. The characteristics of manufactured fibers with trench index profiles are also described. One of the manufactured fibers realizes a bending loss of 0.018 dB/turn at 1550 nm for a bending radius of 7.5 mm, and a splice loss of 0.19 dB at 1550 nm in mechanical splicing to a conventional single mode fiber simultaneously. Other one of the fibers realizes a bending loss of 0.011 dB/turn at 1550 nm for a bending radius of 5 mm, and the splice loss is 0.37 dB at 1550 nm simultaneously. A total loss of a fiber employing the trench index is small and stable against the fluctuation of MFD.

EL (Electroluminescent) displays have been applied to automobiles, as their images are very clear and bright. High voltage, high integration and low power dissipation ICs are needed to drive these devices. To meet this, high voltage CMOS ICs using SOI (Silicon On Insulator) substrates are chosen as the driving devices. In this paper, an isolation structure between the output CMOS devices, of high density and high voltage is proposed. Conventional trench dielectric isolation shows degradation of a break down voltage with short distance from trench to source. In this work, the authors make clear the electric field distribution near the isolation, and offer a novel structure of "Field-plate Trench Isolation," which enables to relax the electric field on the silicon surface by shifting a part of electric field into surface oxide. Finally, operation of high voltage and high density, a 200-volt and 32-channel, EL display driver for automotive display panel is confirmed.

New test structures for evaluating isolation capacitance (CTS) and isolation breakdown voltage (BVCCO) have been developed. Using these test structures, we examined the scaling limit of the width and the structure of narrow isolation U-grooves for high-speed and high-density LSIs. We separated the capacitance CTS into two components, CTSS (bottom component) and CTSL (peripheral component), and analyzed the effect of the device structure (isolation width and filling materials) on CTS. We found that the minimum width of the isolation U-groove is especially limited by the increased isolation capacitance between the neighboring N+ buried layers. The minimum width is about 0.3 µm even when SiO2 is used as a filling material. So we developed an effective method to overcome this limitation. Use of a double-trench structure and/or an SOI substrate meet the requirement. A double-trench structure can reduce CTS by more than 50%, while SOI substrates gives reduced CTS, high BVCCO, high α-ray immunity, and reduced process steps.

High-speed and low-power techniques are described for megabit-class size-configurable CMOS SRAM macrocells. To shorten the design turn-around-time, the methodology of abutting nine kinds of leaf cells is employed; two-level via-hole programming and the array-address decoder embedded in each control leaf cell present a divided-memory-array structure. A new squashed-memory-cell architecture using trench isolation and stacked-via-holes is proposed to reduce access times and power dissipation. To shorten the time for writing data, per-bitline architecture is proposed, in which every bitline has a personal writing driver. Also, read-out circuitry using a current-sense-type two-stage sense amplifier is designed. The effect of the non-multiplexed bitline scheme for fast read-out is shown in a simulation result. To reduce the noise from the second- to first-stage amplifier due to a feedback loop, current paths are separated so as not to cause common impedance. To confirm the techniques described in this paper, a 1-Mb SRAM test chip was fabricated with an advanced 0.35-µm CMOS/bulk process. The SRAM has demonstrated 250-MHz operation with a 2.5-V typical power supply. Also, 100-mW power dissipation was obtained at a practical operating frequency of 150-MHz.

A 7-mask self-aligned SiGe base bipolar transistor has been newly developed. This transistor offers several advancements to a super self-aligned selectively grown SiGe base (SSSB) transistor which has a selectively grown SiGe-base layer formed by a cold-wall ultra high vacuum (UHV)/CVD system. The advancements are as follows: (1) a BPSG-filled arbitrarywidth trench isolation on a SOI is formed by a high-uniformity CMP with a hydro-chuck for reducing the number of isolation fabrication steps, (2) polysilicon-plug emitter and collector electrodes are made simultaneously using an in-situ phosphorusdoped polysilicon film to decrease the distance between emitter and collector electrodes and also to reduce the fabrication steps of the elecrodes, (3) a n+-buried collector layer is made by a high-energy phosphorus ion-implantation technique to eliminate collector epitaxial growth, and (4) a germanium profile in the neutral base region is optimized to increase the fT value without increasing leakage current at the base-cellector junction. In the developed transistor, a high performance of 80-GHz fT and mask-steps reduction are simultaneously achieved.

NAND-structured trench capacitor cell technologies for 256 Mb DRAM and beyond have been developed. The NAND-structured cell has four memory cells connected in series. The cell size can be reduced to 56% of the conventional cell. A substrate plate trench capacitor cell was adapted to this layout. The NAND-structured trench capacitor cell can achieve sufficient storage capacitance within the restricted capacitor area. A sufficient capacitance of 40 fF was achieved when the size and depth of trench were 0.5 µm and 5.0 µm, respectively. The most important point for realizing the NAND-structured trench capacitor cell is how to reduce the leakage current from the storage node. There are two main sources; one is the leakage current to the neighboring cells, the other is the leakage current to Pwell. These leakage currents have been investigated. An experimental 256 Mb DRAM with the NAND-structured cell was fabricated using the 0.4 µm design rule. The chip size is 464 mm2, which is 68% of a conventional DRAM of the same design rule. This is the result of the reduction of the memory cell area by the NAND-structured cell and the introduction of the open-bit-line arrangement.

A new BiCMOS process based on a high-speed bipolar process with 0.5 µm emitter width has been developed using a bonded SOI substrate. Double polysilicon bipolar transistors with the trench isolation, shallow junctions and the pedestal collector implantation provide a high cut-off frequency of 27 GHz. Stress induced device degradation is carefully examined and a low stress trench isolation process is proposed.

A full CMOS cell technology for high density SRAMs has been developed. A 0.4 µm n+/p+ spacing has been achieved by a shallow trench isolation with a retrograde and a shallow well design. Dual gate 0.35 µm n- and p-channel MOSFETs were used for the high density full CMOS SRAM cell. The side-wall inversion problem to which MOSFETs are subject due to the trench isolation structure has been controlled by combining taper angled trench etching and a rounded trench edge shape. A dual gate 0.4 µm nMOS/pMOS spacing has also been accomplished with no lateral gate dopant diffusion by an enlarged grain size tungsten polycide gate structure. These techniques can resolve the bottleneck problem of full CMOS SRAM cell size reduction, and realize a competitive cell size against conventional polysilicon resistor load SRAM cell (E/R type cell) or thin-film-transistor load SRAM cell (TFT type cell) structures. A test chip of a 256 k bit full CMOS SRAM was fabricated to verify the process integration of the shallow trench isolation with the retrograde shallow well design and the dual gate CMOS structure. It has been recognized that the above techniques are possible solutions for deep sub-micron high density full CMOS SRAM cell structure.

Junction leakage current of trench isolation devices is strongly influenced by trench configuration. The origin of the leakage current is the mechanical stress that is generated by the differential thermal expansion between the Si substrate and the SiO2 filled isolation trench during the isolation forming process. A two-dimensional mechanical stress simulation was used to analyze trench-isolated devices. The simulated distribution and magnitude of stress were found to agree with Raman spectroscopic measurements of actual devices. The stress in the deeper regions between deep trenches is likely to increase greatly as the size of devices diminishes, so it is important to reduce this stress and thus suppress junction leakage current.

Localized temperature distribution in silicon on insulator (SOI) structures with trench isolations is calculated using three-dimensional computer simulation. Temperature rise in SOI transistors is about three times higher than in conventional structure transistors because the thermal conductivity of SiO2 is very low. If there are voids in the SiO2 layers and trench isolations, temperature in the SOI transistors increases significantly. A simple model is proposed to calculate steady-state temperature rise in SOI transistors.