A wireless sensor terminal module of 5cc size (2.5 cm × 2.5 cm × 0.8 cm) that does not require a battery is proposed by integrating three kinds of circuit technologies. (i) a low-power sensor interface: an FM modulation type CMOS sensor interface circuit that can operate with a typical power consumption of 24.5 μW was fabricated by the 0.7-μm CMOS process technology. (ii) power supply to the sensor interface circuit: a wireless power transmission characteristic to a small-sized PCB spiral coil antenna was clarified and applied to the module. (iii) wireless sensing from the module: backscatter communication technology that modulates the signal from the base terminal equipment with sensor information and reflects it, which is used for the low-power sensing operation. The module fabricated includes a rectifier circuit with the PCB spiral coil antenna that receives wireless power transmitted from base terminal equipment by electromagnetic resonance coupling and converts it into DC power and a sensor interface circuit that operates using the power. The interface circuit modulates the received signal with the sensor information and reflects it back to the base terminal. The module could achieve 100 mm communication distance when 0.4 mW power is feeding to the sensor terminal.

This paper presents a compact fully-differential distributed amplifier using a coupled inductor. Differential distributed amplifiers are widely required in optical communication systems. Most of the distributed amplifiers reported in the past are single-ended or pseudo-differential topologies. In addition, the differential distributed amplifiers require many inductors, which increases the silicon cost. In this study, we use differentially coupled inductors to reduce the chip area to less than half and eliminate the difficulties in layout design. The challenge in using coupled inductors is the capacitive parasitic coupling that degrades the flatness of frequency response. To address this challenge, the odd-mode image parameters of a differential artificial transmission line are derived using a simple loss-less model. Based on the analytical results, we optimize the dimensions of the inductor with the gradient descent algorithm to achieve accurate impedance matching and phase matching. The amplifier was fabricated in 0.18-µm CMOS technology. The core area of the amplifier is 0.27 mm2, which is 57% smaller than the previous work. Besides, we demonstrated a small group delay variation of ±2.7 ps thanks to the optimization. the amplifier successfully performed 30-Gbps NRZ and PAM4 transmissions with superior jitter performance. The proposed technique will promote the high-density integration of differential traveling wave devices.

Hardware oriented security and trust of semiconductor integrated circuit (IC) chips have been highly demanded. This paper outlines the requirements and recent developments in circuits and packaging systems of IC chips for security applications, with the particular emphasis on protections against physical implementation attacks. Power side channels are of undesired presence to crypto circuits once a crypto algorithm is implemented in Silicon, over power delivery networks (PDNs) on the frontside of a chip or even through the backside of a Si substrate, in the form of power voltage variation and electromagnetic wave emanation. Preventive measures have been exploited with circuit design and packaging technologies, and partly demonstrated with Si test vehicles.

This paper demonstrates that a 360° radio-frequency phase detector consisting of a combination of symmetrical mixers and 45° phase shifters with tunable devices can achieve a low phase-detection error over a wide frequency range. It is shown that the phase detection error does not depend on the voltage gain of the 45° phase shifter. This allows the usage of tunable devices as 45° phase shifters for a wide frequency range with low phase-detection errors. The fabricated phase detector having tunable low-pass filters as the tunable device demonstrates phase detection errors lower than 2.0° rms in the frequency range from 3.0 GHz to 10.5 GHz.

This paper presents low-noise amplifier (LNA)-less 300-GHz CMOS receivers that operate above the NMOS unity-power-gain frequency, fmax. The receivers consist of a down-conversion mixer with a doubler- or tripler-last multiplier chain that upconverts an LO1/n signal into 300 GHz. The conversion gain of the receiver with the doubler-last multiplier is -19.5 dB and its noise figure, 3-dB bandwidth, and power consumption are 27 dB, 27 GHz, and 0.65 W, respectively. The conversion gain of the receiver with the tripler-last multiplier is -18 dB and its noise figure, 3-dB bandwidth, and power consumption are 25.5 dB, 33 GHz, and 0.41 W, respectively. The receivers achieve a wireless data rate of 32 Gb/s with 16QAM. This shows the potential of the moderate-fmax CMOS technology for ultrahigh-speed THz wireless communications.

A 15GHz-band 4-channel transmit/receive RF core-chip is presented for high SHF wide-band massive MIMO in 5G. In order to realize small RF frontend for 5G base stations, both 6bit phase shifters (PS) and 0.25 dB resolution variable gain amplifiers (VGA) are integrated in TX and RX paths of 4-channels on the chip. A PS calibration technique is applied to compensate the error of 6bit PS caused by process variations. A common gate current steering topology with tail current control is used for VGA to enhance the gain control accuracy. The 15GHz-band RF core-chip fabricated in 65 nm CMOS process achieved phase control error of 1.9deg. rms., and amplitude control error of 0.23 dB. rms.

A 150 MS/s 10-bit MOS-inverter-based subranging analog-to-digital converter (ADC) dedicated to a high-speed low-power application is presented in this paper. A new time constant reduction technique is proposed in the multi-stage preamplifier design which aims to further increase the speed of the coarse ADC. A synchronized switch is introduced to minimize the sample-time mismatch in the interleaved architecture of fine ADCs. An internal pipelined scheme incorporating the double sampling and interleaving techniques in fine ADCs allows the ADC sample input signal to run on a consecutive clock, thus maximizing the throughput. The prototype ADC achieves 52 dB SNDR for a 10 MHz input frequency at 150 MS/s. Without calibration, the measured differential nonlinearity (DNL) is 0.5 LSB, while the integral nonlinearity (INL) is 0.9 LSB. The CMOS ADC is fabricated in a 0.35 µm CMOS technology, with an active area of 2.7 mm2, consuming only 178 mW from a single 3 V supply. Comparing technology normalized figure-of-merits, it achieves better power-speed efficiency than other similar types of ADCs.

A single-chip ubiquitous sensor network (USN) system-on-a-chip (SoC) for small program memory size and low power has been proposed and integrated in a 0.18-µm CMOS technology. Proposed single-chip USN SoC is mainly consists of radio for 868/915 MHz, analog building block, complete digital baseband physical layer (PHY) and media access control (MAC) functions. The transceiver's analog building block includes a low-noise amplifier, mixer, channel filter, receiver signal-strength indication, frequency synthesizer, voltage-controlled oscillator, and power amplifier. In addition, digital building block consists of differential binary phase-shift keying (DPSK) modulation, demodulation, carrier frequency offset compensation, auto-gain control, embedded 8-bit microcontroller, and digital MAC function. Digital MAC function supports 128 bit advanced encryption standard (AES), cyclic redundancy check (CRC), inter-symbol timing check, MAC frame control, and automatic retransmission. These digital MAC functions reduce the processing power requirements of embedded microcontroller and program memory size by up to 56%. The cascaded noise figure and sensitivity of the overall receiver are 9.5 dB and -99 dBm, respectively. The overall transmitter achieves less than 6.3% error vector magnitude (EVM). The current consumption is 14 mA for reception mode and 16 mA for transmission mode.

A linear CMOS transconductor is presented. PMOS transistors are employed in the resistor-replacement and voltage-level shifting to avoid the body effect. To annihilate the non-linear voltage terms, the substrate-bias effect of MOS transistors is treated more accurately in our design. Consequently, the non-linearity of the large-signal transconductance is reduced. The fabricated circuit occupies an area of 245 µm176 µm ( ≈approx 0.043 mm2) and dissipates 0.87 mW from a 3.3 V supply. For an input of 1 Vp-p, the measured output total harmonic distortion is less than 1.2%. The transconductance varies by less than 0.5% in the input range.

This paper presents a high performance wideband CMOS direct down-conversion mixer for UWB based on 0.18 µm CMOS technology. The proposed mixer uses the current bleeding technique and an extra resonant inductor to improve the conversion gain, noise figure (NF) and linearity. Also, with an extra inductor and the careful choosing of transistor sizes, the mixer has a very low flicker noise. The shunt resistor matching is applied to have a 528 MHz bandwidth matching at 50 Ohm. The simulation results show the voltage conversion gain of 20.5 dB, the double-side band NF of 5.6 dB. Two-tone test result indicates 11.25 dBm of IIP3 and higher than 70 dBm of IIP2. The circuit operates at the supply voltage of 1.8 V, and dissipates 11.5 mW.

This paper presents a second-generation CMOS current conveyor (CCII) consisting of a rail-to-rail complementary n- and p-channel differential input stage for the voltage input, a class AB push-pull stage for the current input, and current mirrors for the current outputs. The CCII was implemented using a double-poly triple-metal 0.6 µm n-well CMOS process, to confirm its operation experimentally. A prototype chip achieves a rail-to-rail swing 2.3 V under 2.5 V power supplies and shows the exact voltage and current following performances up to 100 MHz. Because of its high performances, the CCII proposed herein is quite useful for a building block of current-mode circuits.

The second-generation CMOS current conveyors are developed for high-frequency analog signal processing. It consists of a source follower for the voltage input and a regulated current mirror for the current input and output. The voltage and current input stages are also coupled by a current mirror to reduce the impedance of the current input port. Simulations show that this architecture provides the high input/output conductance ratio and the inherent voltage and current transfer bandwidths extending beyond 100 MHz. The prototype chips fabricated using 0. 6 µm CMOS process have confirmed the simulated performances, though the voltage and current bandwidth are limited to 20 MHz and 35 MHz, respectively, by the built-in capacitances of the bonding pads.