Substrate-Noise and Random-Variability Reduction with Self-Adjusted Forward Body Bias

Yoshihide KOMATSU; Koichiro ISHIBASHI; Makoto NAGATA

doi:10.1093/ietele/e90-c.4.692

Substrate-Noise and Random-Variability Reduction with Self-Adjusted Forward Body Bias

Yoshihide KOMATSU, Koichiro ISHIBASHI, Makoto NAGATA

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This paper describes a method of reducing substrate noise and random variability utilizing a self-adjusted forward body bias (SA-FBB) circuit. To achieve this, we designed a test chip (130 nm CMOS 3-well) that contained an on-chip oscilloscope for detecting dynamic noise from various frequency noise sources, and another test chip (90 nm CMOS 2-well) that contained 10-M transistors for measuring random variability tendencies. Under SA-FBB conditions, it reduced noise by 35.3-69.8% and reduced random variability σ (I_ds) by 23.2-57.9%.

Publication: IEICE TRANSACTIONS on Electronics Vol.E90-C No.4 pp.692-698

Publication Date: 2007/04/01

Publicized

Online ISSN: 1745-1353

DOI: 10.1093/ietele/e90-c.4.692

Type of Manuscript: Special Section PAPER (Special Section on Low-Power, High-Speed LSIs and Related Technologies)

Category: Digital

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Yoshihide KOMATSU, Koichiro ISHIBASHI, Makoto NAGATA, "Substrate-Noise and Random-Variability Reduction with Self-Adjusted Forward Body Bias" in IEICE TRANSACTIONS on Electronics, vol. E90-C, no. 4, pp. 692-698, April 2007, doi: 10.1093/ietele/e90-c.4.692.
Abstract: This paper describes a method of reducing substrate noise and random variability utilizing a self-adjusted forward body bias (SA-FBB) circuit. To achieve this, we designed a test chip (130 nm CMOS 3-well) that contained an on-chip oscilloscope for detecting dynamic noise from various frequency noise sources, and another test chip (90 nm CMOS 2-well) that contained 10-M transistors for measuring random variability tendencies. Under SA-FBB conditions, it reduced noise by 35.3-69.8% and reduced random variability σ (I_ds) by 23.2-57.9%.
URL: https://globals.ieice.org/en_transactions/electronics/10.1093/ietele/e90-c.4.692/_p

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@ARTICLE{e90-c_4_692,
author={Yoshihide KOMATSU, Koichiro ISHIBASHI, Makoto NAGATA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Substrate-Noise and Random-Variability Reduction with Self-Adjusted Forward Body Bias},
year={2007},
volume={E90-C},
number={4},
pages={692-698},
abstract={This paper describes a method of reducing substrate noise and random variability utilizing a self-adjusted forward body bias (SA-FBB) circuit. To achieve this, we designed a test chip (130 nm CMOS 3-well) that contained an on-chip oscilloscope for detecting dynamic noise from various frequency noise sources, and another test chip (90 nm CMOS 2-well) that contained 10-M transistors for measuring random variability tendencies. Under SA-FBB conditions, it reduced noise by 35.3-69.8% and reduced random variability σ (I_ds) by 23.2-57.9%.},
keywords={},
doi={10.1093/ietele/e90-c.4.692},
ISSN={1745-1353},
month={April},}

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TY - JOUR
TI - Substrate-Noise and Random-Variability Reduction with Self-Adjusted Forward Body Bias
T2 - IEICE TRANSACTIONS on Electronics
SP - 692
EP - 698
AU - Yoshihide KOMATSU
AU - Koichiro ISHIBASHI
AU - Makoto NAGATA
PY - 2007
DO - 10.1093/ietele/e90-c.4.692
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E90-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2007
AB - This paper describes a method of reducing substrate noise and random variability utilizing a self-adjusted forward body bias (SA-FBB) circuit. To achieve this, we designed a test chip (130 nm CMOS 3-well) that contained an on-chip oscilloscope for detecting dynamic noise from various frequency noise sources, and another test chip (90 nm CMOS 2-well) that contained 10-M transistors for measuring random variability tendencies. Under SA-FBB conditions, it reduced noise by 35.3-69.8% and reduced random variability σ (I_ds) by 23.2-57.9%.
ER -