Low-Power On-Chip Supply Voltage Conversion Scheme for Ultrahigh-Density DRAM's

Daisaburo TAKASHIMA; Shigeyoshi WATANABE; Tsuneaki FUSE; Kazumasa SUNOUCHI; Takahiko HARA

Low-Power On-Chip Supply Voltage Conversion Scheme for Ultrahigh-Density DRAM's

Daisaburo TAKASHIMA, Shigeyoshi WATANABE, Tsuneaki FUSE, Kazumasa SUNOUCHI, Takahiko HARA

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In order to achieve 3.3-V 1-Gb DRAM and beyond, this paper proposes a new on-chip supply voltage conversion scheme, which converts 3.3-V external supply voltage V_ext to lowered 1.5-V internal supply voltage V_int without any power loss within the voltage converter. This scheme connects two identical DRAM circuits in series between V_ext and V_ss. By operations of two DRAM circuits with the same clock timing, the voltage between two DRAM's, V_int, is automatically fixed to 1/2V_ext. Therefore, each upper and lower DRAM circuit can operate at lowered 1/2V_ext without use of the conventional voltage converter. This scheme was successfully verified by an experimental system using 4-Mb DRAM's. Utilizing the proposed scheme, power dissipation was reduced by as much as 50% and stable operation was achieved without access speed penalty.

Publication: IEICE TRANSACTIONS on Electronics Vol.E76-C No.5 pp.844-849

Publication Date: 1993/05/25

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Type of Manuscript: Special Section PAPER (Special Section on the 1992 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.28, No.4 April 1993))

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Daisaburo TAKASHIMA
Shigeyoshi WATANABE
Tsuneaki FUSE
Kazumasa SUNOUCHI
Takahiko HARA

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Daisaburo TAKASHIMA, Shigeyoshi WATANABE, Tsuneaki FUSE, Kazumasa SUNOUCHI, Takahiko HARA, "Low-Power On-Chip Supply Voltage Conversion Scheme for Ultrahigh-Density DRAM's" in IEICE TRANSACTIONS on Electronics, vol. E76-C, no. 5, pp. 844-849, May 1993, doi: .
Abstract: In order to achieve 3.3-V 1-Gb DRAM and beyond, this paper proposes a new on-chip supply voltage conversion scheme, which converts 3.3-V external supply voltage V_ext to lowered 1.5-V internal supply voltage V_int without any power loss within the voltage converter. This scheme connects two identical DRAM circuits in series between V_ext and V_ss. By operations of two DRAM circuits with the same clock timing, the voltage between two DRAM's, V_int, is automatically fixed to 1/2V_ext. Therefore, each upper and lower DRAM circuit can operate at lowered 1/2V_ext without use of the conventional voltage converter. This scheme was successfully verified by an experimental system using 4-Mb DRAM's. Utilizing the proposed scheme, power dissipation was reduced by as much as 50% and stable operation was achieved without access speed penalty.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/e76-c_5_844/_p

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@ARTICLE{e76-c_5_844,
author={Daisaburo TAKASHIMA, Shigeyoshi WATANABE, Tsuneaki FUSE, Kazumasa SUNOUCHI, Takahiko HARA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Low-Power On-Chip Supply Voltage Conversion Scheme for Ultrahigh-Density DRAM's},
year={1993},
volume={E76-C},
number={5},
pages={844-849},
abstract={In order to achieve 3.3-V 1-Gb DRAM and beyond, this paper proposes a new on-chip supply voltage conversion scheme, which converts 3.3-V external supply voltage V_ext to lowered 1.5-V internal supply voltage V_int without any power loss within the voltage converter. This scheme connects two identical DRAM circuits in series between V_ext and V_ss. By operations of two DRAM circuits with the same clock timing, the voltage between two DRAM's, V_int, is automatically fixed to 1/2V_ext. Therefore, each upper and lower DRAM circuit can operate at lowered 1/2V_ext without use of the conventional voltage converter. This scheme was successfully verified by an experimental system using 4-Mb DRAM's. Utilizing the proposed scheme, power dissipation was reduced by as much as 50% and stable operation was achieved without access speed penalty.},
keywords={},
doi={},
ISSN={},
month={May},}

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TY - JOUR
TI - Low-Power On-Chip Supply Voltage Conversion Scheme for Ultrahigh-Density DRAM's
T2 - IEICE TRANSACTIONS on Electronics
SP - 844
EP - 849
AU - Daisaburo TAKASHIMA
AU - Shigeyoshi WATANABE
AU - Tsuneaki FUSE
AU - Kazumasa SUNOUCHI
AU - Takahiko HARA
PY - 1993
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E76-C
IS - 5
JA - IEICE TRANSACTIONS on Electronics
Y1 - May 1993
AB - In order to achieve 3.3-V 1-Gb DRAM and beyond, this paper proposes a new on-chip supply voltage conversion scheme, which converts 3.3-V external supply voltage V_ext to lowered 1.5-V internal supply voltage V_int without any power loss within the voltage converter. This scheme connects two identical DRAM circuits in series between V_ext and V_ss. By operations of two DRAM circuits with the same clock timing, the voltage between two DRAM's, V_int, is automatically fixed to 1/2V_ext. Therefore, each upper and lower DRAM circuit can operate at lowered 1/2V_ext without use of the conventional voltage converter. This scheme was successfully verified by an experimental system using 4-Mb DRAM's. Utilizing the proposed scheme, power dissipation was reduced by as much as 50% and stable operation was achieved without access speed penalty.
ER -