A new memory cell array structure for high density DRAMs is proposed. This new structure is superior to both conventional open bit line and folded bit line structures when the use of isolation merged trench cells, such as FC cell, are considered. The application of this structure to a 16 M bit DRAM cell array design will be also discussed.

In order to achieve 3.3-V 1-Gb DRAM and beyond, this paper proposes a new on-chip supply voltage conversion scheme, which converts 3.3-V external supply voltage Vext to lowered 1.5-V internal supply voltage Vint without any power loss within the voltage converter. This scheme connects two identical DRAM circuits in series between Vext and Vss. By operations of two DRAM circuits with the same clock timing, the voltage between two DRAM's, Vint, is automatically fixed to 1/2Vext. Therefore, each upper and lower DRAM circuit can operate at lowered 1/2Vext without use of the conventional voltage converter. This scheme was successfully verified by an experimental system using 4-Mb DRAM's. Utilizing the proposed scheme, power dissipation was reduced by as much as 50% and stable operation was achieved without access speed penalty.

An ultra low voltage CMOS pass-gate logic using body-bias controlled SOI MOSFETs has been developed. The logic is composed of gate-body connected SOI pass-gates and a CMOS buffer with the body-bias controlled by the complementary double-rail input. The full-adder using the proposed logic improved the lowest operation voltage by 27%, compared with the SOI CPL (Complementary Pass-Gate Logic). For a 16 16 bit multiplier, the power-delay product achieved 70 pJ (including 50 pF I/O) at 0.5 V power supply, which was more than 1 order of magnitude improvement over the bulk CPL.