A Shared Multibuffer Architecture for High-Speed ATM Switch LSIs

Harufusa KONDOH; Hiromi NOTANI; Hideaki YAMANAKA; Keiichi HIGASHITANI; Hirotaka SAITO; Isamu HAYASHI; Yoshio MATSUDA; Kazuyoshi OSHIMA; Masao NAKAYA

A Shared Multibuffer Architecture for High-Speed ATM Switch LSIs

Harufusa KONDOH, Hiromi NOTANI, Hideaki YAMANAKA, Keiichi HIGASHITANI, Hirotaka SAITO, Isamu HAYASHI, Yoshio MATSUDA, Kazuyoshi OSHIMA, Masao NAKAYA

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A new shared multibuffer architecture for high-speed ATM (Asynchronous Transfer Mode) switch LSIs is described. Multiple buffer memories are located between two crosspoint switches. By controlling the input-side crosspoint switch so as to equalize the utilization rate of each buffer memory, these multiple buffer memories can be recognized as a single large shared buffer memory. High utilization efficiency of buffer memory can thus be achieved, and the cell loss ratio is minimized. By accessing the buffer memories in parallel via crosspoint switches, the time required to access the buffer memories is greatly reduced. This feature enables high-speed operation of the switch. The shared multibuffer architecture was implemented in a switch LSI using 0.8-µm BiCMOS process technology. Experimental results revealed that this chip can operate at more than 125 MHz. Bit-sliced eight switch LSIs operating at 78 MHz construct a 622-Mb/s 88 ATM switching system with a buffer size of 1,024 ATM cells. Power consumption of the switch LSI was 3 W.

Publication: IEICE TRANSACTIONS on Electronics Vol.E76-C No.7 pp.1094-1101

Publication Date: 1993/07/25

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Type of Manuscript: Special Section PAPER (Special Issue on New Architecture LSIs)

Category: Improved Binary Digital Architectures

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Harufusa KONDOH, Hiromi NOTANI, Hideaki YAMANAKA, Keiichi HIGASHITANI, Hirotaka SAITO, Isamu HAYASHI, Yoshio MATSUDA, Kazuyoshi OSHIMA, Masao NAKAYA, "A Shared Multibuffer Architecture for High-Speed ATM Switch LSIs" in IEICE TRANSACTIONS on Electronics, vol. E76-C, no. 7, pp. 1094-1101, July 1993, doi: .
Abstract: A new shared multibuffer architecture for high-speed ATM (Asynchronous Transfer Mode) switch LSIs is described. Multiple buffer memories are located between two crosspoint switches. By controlling the input-side crosspoint switch so as to equalize the utilization rate of each buffer memory, these multiple buffer memories can be recognized as a single large shared buffer memory. High utilization efficiency of buffer memory can thus be achieved, and the cell loss ratio is minimized. By accessing the buffer memories in parallel via crosspoint switches, the time required to access the buffer memories is greatly reduced. This feature enables high-speed operation of the switch. The shared multibuffer architecture was implemented in a switch LSI using 0.8-µm BiCMOS process technology. Experimental results revealed that this chip can operate at more than 125 MHz. Bit-sliced eight switch LSIs operating at 78 MHz construct a 622-Mb/s 88 ATM switching system with a buffer size of 1,024 ATM cells. Power consumption of the switch LSI was 3 W.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/e76-c_7_1094/_p

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@ARTICLE{e76-c_7_1094,
author={Harufusa KONDOH, Hiromi NOTANI, Hideaki YAMANAKA, Keiichi HIGASHITANI, Hirotaka SAITO, Isamu HAYASHI, Yoshio MATSUDA, Kazuyoshi OSHIMA, Masao NAKAYA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Shared Multibuffer Architecture for High-Speed ATM Switch LSIs},
year={1993},
volume={E76-C},
number={7},
pages={1094-1101},
abstract={A new shared multibuffer architecture for high-speed ATM (Asynchronous Transfer Mode) switch LSIs is described. Multiple buffer memories are located between two crosspoint switches. By controlling the input-side crosspoint switch so as to equalize the utilization rate of each buffer memory, these multiple buffer memories can be recognized as a single large shared buffer memory. High utilization efficiency of buffer memory can thus be achieved, and the cell loss ratio is minimized. By accessing the buffer memories in parallel via crosspoint switches, the time required to access the buffer memories is greatly reduced. This feature enables high-speed operation of the switch. The shared multibuffer architecture was implemented in a switch LSI using 0.8-µm BiCMOS process technology. Experimental results revealed that this chip can operate at more than 125 MHz. Bit-sliced eight switch LSIs operating at 78 MHz construct a 622-Mb/s 88 ATM switching system with a buffer size of 1,024 ATM cells. Power consumption of the switch LSI was 3 W.},
keywords={},
doi={},
ISSN={},
month={July},}

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TY - JOUR
TI - A Shared Multibuffer Architecture for High-Speed ATM Switch LSIs
T2 - IEICE TRANSACTIONS on Electronics
SP - 1094
EP - 1101
AU - Harufusa KONDOH
AU - Hiromi NOTANI
AU - Hideaki YAMANAKA
AU - Keiichi HIGASHITANI
AU - Hirotaka SAITO
AU - Isamu HAYASHI
AU - Yoshio MATSUDA
AU - Kazuyoshi OSHIMA
AU - Masao NAKAYA
PY - 1993
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E76-C
IS - 7
JA - IEICE TRANSACTIONS on Electronics
Y1 - July 1993
AB - A new shared multibuffer architecture for high-speed ATM (Asynchronous Transfer Mode) switch LSIs is described. Multiple buffer memories are located between two crosspoint switches. By controlling the input-side crosspoint switch so as to equalize the utilization rate of each buffer memory, these multiple buffer memories can be recognized as a single large shared buffer memory. High utilization efficiency of buffer memory can thus be achieved, and the cell loss ratio is minimized. By accessing the buffer memories in parallel via crosspoint switches, the time required to access the buffer memories is greatly reduced. This feature enables high-speed operation of the switch. The shared multibuffer architecture was implemented in a switch LSI using 0.8-µm BiCMOS process technology. Experimental results revealed that this chip can operate at more than 125 MHz. Bit-sliced eight switch LSIs operating at 78 MHz construct a 622-Mb/s 88 ATM switching system with a buffer size of 1,024 ATM cells. Power consumption of the switch LSI was 3 W.
ER -