Current resonance type of LLC converter is widely used owing to their low switching losses; however, the problem is that they have a large transformer loss. We examine the reduction of AC resistance of the transformer winding and high coupling between the primary and secondary windings of the transformer, as a method for reducing the copper loss. In this case, it is necessary to consider the effects of the increase in stray capacitance between the primary and secondary windings of the transformer. This paper describes the influence of the loss due to the capacitance generated between the transformer windings when a noise filter is connected to the LLC converter. Furthermore, we propose a new method for reducing loss by connecting a bridge-capacitor between the primary and secondary sides of the transformer. The results of the new method are shown, and compared with those of the simulations to demonstrate effectiveness.

A novel charge pump, Capacitance Varying Charge Pump (CVCP) is proposed. This charge pump is composed of variable capacitors and rectifiers, and the charge transfer is attained by changing the capacitance values in a manner similar to peristaltic pumps. The analysis of multi-stage CVCP reveals that the output voltage is exponentially dependent on the stage number. Thus, compared with the Dickson charge pump, this charge pump has an advantage in generating high voltages with small stages. As a practical example of CVCP, we present an implementation realized by a MEMS (Micro-Electro-Mechanical Systems) technology. Here, the variable capacitor is enabled by a comb-capacitor attached to a high-quality factor resonator. As the rectifier, a PN-junction diode formed in the MEMS layer is used. Simulations including the mechanical elements are carried out for this MEMS version of CVCP. The simulation results on the output voltage and load characteristics are shown to coincide well with the theoretical estimations. The MEMS CVCP is suited for MEMS devices and vibration energy harvesters.

An ESL-cancelling circuit for a shunt-connected film capacitor filter using vertically stacked coupled square loops is reported in this paper. The circuit is applicable for a shunt-connected capacitor filter whose equivalent series inductance (ESL) of the shunt-path causes deterioration of filter performance at frequencies above the self-resonant frequency. Two pairs of vertically stacked magnetically coupled square loops are used in the circuit those can equivalently add negative inductance in series to the shunt-path to cancel ESL for improvement of the filter performance. The ESL-cancelling circuit for a 1-μF film capacitor was designed according to the Biot-Savart law and electromagnetic (EM)-analysis, and the prototype was fabricated with an FR4 substrate. The measured result showed 20-dB improvement of the filter performance above the self-resonant frequency as designed, satisfying Sdd21 less than -40dB at 1MHz to 100MHz. This result is almost equivalent to reduce ESL of the shunt-path to less than 1nH at 100MHz and is also difficult to realize using any kind of a single bulky film capacitor without cancelling ESL.

Energy harvesting has been widely investigated as a potential solution to supply power for Internet of Things (IoT) devices. Computing devices must operate intermittently rather than continuously, because harvested energy is unstable and some of IoT applications can be periodic. Therefore, processors for IoT devices with intermittent operation must feature a hibernation mode with zero-standby-power in addition to energy-efficient normal mode. In this paper, we describe the layout design and measurement results of a nonvolatile standard cell memory (NV-SCM) and nonvolatile flip-flops (NV-FF) with a nonvolatile memory using Fishbone-in-Cage Capacitor (FiCC) suitable for IoT processors with intermittent operations. They can be fabricated in any conventional CMOS process without any additional mask. NV-SCM and NV-FF are fabricated in a 180nm CMOS process technology. The area overhead by nonvolatility of a bit cell are 74% in NV-SCM and 29% in NV-FF, respectively. We confirmed full functionality of the NV-SCM and NV-FF. The nonvolatile system using proposed NV-SCM and NV-FF can reduce the energy consumption by 24.3% compared to the volatile system when hibernation/normal operation time ratio is 500 as shown in the simulation.

A fully analog pipelined deep neural network (DNN) accelerator is proposed, which is constructed by using pipeline registers based on master-slave switched capacitors. The idea of the master-slave switched capacitors is an analog equivalent of the delayed flip-flop (D-FF) which has been used as a digital pipeline register. To estimate the performance of the pipeline register, it is applied to a conventional DNN which performs non-pipeline operation. Compared with the conventional DNN, the cycle time is reduced by 61.5% and data rate is increased by 160%. The accuracy reaches 99.6% in MNIST classification test. The energy consumption per classification is reduced by 88.2% to 0.128µJ, achieving an energy efficiency of 1.05TOPS/W and a throughput of 0.538TOPS in 180nm technology node.

This paper presents a Ka-band high-efficiency power amplifier (PA) with a novel adaptively controlled gate capacitor circuit and a two-step adaptive bias circuit for 5th generation (5G) mobile terminal applications fabricated using a 45-nm silicon on insulator (SOI) CMOS process. The PA adopts a stacked FET structure to increase the output power because of the low breakdown voltage issue of scaled MOSFETs. The novel adaptive gate capacitor circuit properly controls the RF swing for each stacked FET to achieve high efficiency in the several-dB back-off region. Further, the novel two-step adaptive bias circuit effectively controls the gate voltage for each stacked FET for high linearity and high back-off efficiency. At a supply voltage of 4 V, the fabricated PA has exhibited a saturated output power of 20.0 dBm, a peak power added efficiency (PAE) of 42.7%, a 3dB back-off efficiency of 32.7%, a 6dB back-off efficiency of 22.7%, and a gain of 15.6 dB. The effective PA area was 0.82 mm by 0.74 mm.

This paper proposes a design of high-speed interconnection between optical modules and electrical modules via bonding-wires and coplanar waveguide transmission lines on printed circuit boards for 400 Gbps 4-channel optical communication systems. In order to broaden the interconnection bandwidth, interdigitated capacitors were integrated with GSG pads on chip for the first time. Simulation results indicate the reflection coefficient is below -10 dB from DC to 53 GHz and the insertion loss is below 1 dB from DC to 45 GHz. Both indicators show that the proposed interconnection structure can effectively satisfy the communication bandwidth requirements of 100-Gbps or even higher data-rate PAM4 signals.

The resistor variation can severely affect current reference sources, which may vary up to ±40% in scaled CMOS processes. In addition, such variations make the opamp design challenging and increase the design margin, impacting power consumption. This paper proposes a Time-Based Current Source (TBCS): a robust and process-scalable reference current source suitable for switched-capacitor (SC) circuits. We construct a delay-locked-loop (DLL) to lock the current-starved inverter with the reference clock, enabling the use of the settled current directly as a reference current. Since the load capacitors determine the delay, the generated current is decoupled from resistor values and enables a robust reference current source. The prototype TBCS fabricated in 28nm CMOS achieved a minimal area of 1200um2. The current variation is suppressed to half compared to BGR based current sources, confirmed in extensive PVT variation simulations. Moreover, when used as the opamp's bias, TBCS achieves comparable opamp GBW to an ideal current source.

Aluminum Electrolytic Capacitors are widely used as the smoothing capacitors in power converter circuits. Recently, there are a lot of studies to detect the residual life of the smoothing Aluminum Electrolytic Capacitors from the information of the operational circuit, such as the ripple voltage and the ripple current of the smoothing capacitor. To develop this kind of technology, more precise impedance models of Aluminum Electrolytic Capacitors become desired. In the case of the low-temperature operation of the power converters, e.g., photovoltaic inverters, the impedance of the smoothing Aluminum Electrolytic Capacitor is the key to avoid the switching element failure due to the switching surge. In this paper, we introduce the impedance calculation model of Aluminum Electrolytic Capacitors, which provides accurate impedance values in wide temperature and frequency ranges.

This paper proposes a dual-polarized metasurface that utilizes multi-layer ceramic capacitors (MLCCs) for radar cross-section (RCS) reduction in the 28GHz band of the quasi-millimeter band. MLCCs are very small in size; therefore, miniaturization of the unit cell structure of the metamaterial can be expected, and the MLCCs can be periodically loaded onto a narrow object. First, the MLCC structure was modeled as a basic structure, and the effective permeability of the MLCC was determined to investigate the influence of the arrangement direction on MLCC interaction. Next, the unit cell structure of the dual-polarized metasurface was designed for an MLCC set on a dielectric substrate. By analyzing the infinite periodic structure and finite structure, the monostatic reduction characteristics, oblique incidence characteristics, and dual-polarization characteristics of the proposed metasurface were evaluated. In the case of the MLCCs arranged in the same direction, the monostatic RCS reduction was approximately 30dB at 29.8GHz, and decreased when the MLCCs were arranged in a checkerboard pattern. The monostatic RCS reductions for the 5 × 5, 10 × 10, and 20 × 20 divisions were roughly the same, i.e., 10.8, 9.9, and 10.3dB, respectively. Additionally, to validate the simulated results, the proposed dual-polarized metasurface was fabricated and measured. The measured results were found to approximately agree with the simulated results, confirming that the RCS can be reduced for dual-polarization operation.

This paper presents a novel delta-sigma modulator that uses a switched-capacitor (SC) integrator with the structure of a finite impulse response (FIR) filter in a loop filter configuration. The delta-sigma analog-to-digital converter (ΔΣADC) is used in various conversion systems to enable low-power, high-accuracy conversion using oversampling and noise shaping. Increasing the gain coefficient of the integrator in the loop filter configuration of the ΔΣADC suppresses the quantization noise that occurs in the signal band. However, there is a trade-off relationship between the integrator gain coefficient and system stability. The SC integrator, which contains an FIR filter, can suppress quantization noise in the signal band without requiring an additional operational amplifier. Additionally, it can realize a higher signal-to-quantization noise ratio. In addition, the poles that are added by the FIR filter structure can improve the system's stability. It is also possible to improve the flexibility of the pole placement in the system. Therefore, a noise transfer function that does not contain a large gain peak is realized. This results in a stable system operation. This paper presents the essential design aspects of a ΔΣADC with an FIR filter. Two types of simulation results are examined for the proposed first- and second-order, and these results confirm the effectiveness of the proposed architecture.

A 2nd-order ΔΣAD modulator architecture is proposed to simplify the operation phase using ring amplifier and SAR quantizer. The proposed modulator architecture can guarantee the reset time for ring amplifier and relax the speed requirement on asynchronous SAR quantizer. The SPICE simulation results demonstrate the feasibility of the proposed 2nd-order ΔΣAD modulator in 90nm CMOS technology. Simulated SNDR of 95.70dB is achieved while a sinusoid -1dBFS input is sampled at 60MS/s for the bandwidth is BW=470kHz. The power consumption of the analog part in the modulator is 1.67mW while the supply voltage is 1.2V.

In this work, the metal-oxide-metal (MOM) capacitor in the scaled CMOS process has been modeled at high frequencies using an EM simulator, and its layout has been optimized. The modeled parasitic resistance consists of four components, and the modeled parasitic inductance consists of the comb inductance and many mutual inductances. Each component of the parasitic resistance and inductance show different degrees of dependence on the finger length and on the number of fingers. The substrate network parameters also have optimum points. As such, the geometric dependence of the characteristics of the MOM capacitor is investigated and the optimum layout in the constant-capacitance case is proposed by calculating the results of the model. The proposed MOM capacitor structures for 50fF at f =60GHz are L =5μm with M =3, and, L =2μm with M =5 and that for 100fF at f =30GHz are L =9μm with M =3, and L =4μm with M =5. The target process is 65-nm CMOS.

This work develops a third-order multibit switched-current (SI) delta-sigma modulator (DSM) with a four-bit switched-capacitor (SC) flash analog-to-digital converter (ADC) and an incremental data weighted averaging circuit (IDWA), which is fabricated using 0.18µm 1P6M CMOS technology. In the proposed DSM, a 4-bit SC flash ADC is used to improve its resolution, and an IDWA is used to reduce the nonlinearity of digital-to-analog converter (DAC) by moving the quantization noise out of the signal band by first-order noise shaping. Additionally, the proposed differential sample-and-hold circuit (SH) exhibits low input impedance with feedback and width-length adjustment in the SI feedback memory cell (FMC) to increase the conversion rate. A coupled differential replicate (CDR) common-mode feedforward circuit (CMFF) is used to compensate for the mirror error that is caused by the current mirror. Measurements indicate that the signal-to-noise ratio (SNR), dynamic range (DR), effective number of bits (ENOB), power consumption, and chip area are 64.1 dB, 64.4 dB, 10.36 bits, 18.82 mW, and 0.45 × 0.67 mm2 (without I/O pad), respectively, with a bandwidth of 20 kHz, an oversampling ratio (OSR) of 256, a sampling frequency of 10.24 MHz, and a supply voltage of 1.8 V.

Mixed-signal integrated circuit design and simulation highly rely on behavioral models of circuit blocks. Such models are used for the validation of design specification, optimization of system topology, and behavioral synthesis using a description language, etc. However, automatic behavioral model generation is still in its early stages; in most scenarios designers are responsible for creating behavioral models manually, which is time-consuming and error prone. In this paper an automatic behavioral model generation method for switched-capacitor (SC) integrator is proposed. This technique is based on symbolic circuit modeling with approximation, by which parametric behavioral integrator model can be generated. Such parametric models can be used in circuit design subject to severe process variational. It is demonstrated that the automatically generated integrator models can accurately capture process variation effects on arbitrarily selected circuit elements; furthermore, they can be applied to behavioral simulation of SC Sigma-Delta modulators (SDMs) with acceptable accuracy and speedup. The generated models are compared to a recently proposed manually generated behavioral integrator model in several simulation settings.

Noise and area consumption has been a trade-off in circuit design. Especially for switched-capacitor filters (SCF), kT/C noise gives a limitation to the minimum value of unit capacitance. In case of SCFs with a large capacitance spread, this limitation will result in a large area consumption due to large capacitors. This paper introduces a technique to reduce capacitance spread using charge scaling. It will be shown that this technique can reduce total capacitance of SCFs without deteriorating their noise performances. A design method to reduce the output noise of SC low-pass filters (LPF) based on the combination of cut-set scaling, charge scaling and adaptive configuration is proposed. The proposed technique can reduce the output noise voltage by 30% for small input signals.

Liquid crystal displays (LCDs) are suitable as elements underlying wearable and ubiquitous computing thanks to their low power consumption. A technique that uses less power to drive 1-pixel LCDs is proposed. It harvests the charges on the LCD and stores them in an external capacitor for reuse when the polarity changes. A simulation shows that the charge reduction depends on the ratio of the capacitance of the external capacitor to that of the LCD and can reach 50%. An experiment on a prototype demonstrates an almost 30% reduction with large 1-pixel LCDs. With a small 10 × 10mm2 LCD, the overhead of the micro-controller matches the reduction so no improvement could be measured. Though the technique requires longer time for polarity reversal, we confirm that it does not significantly degrade visual quality.

This paper demonstrates the resonant power supply noise reduction effects of STO thin film decoupling capacitors, which are embedded in interposers. The on-interposer STO capacitor consists of SrTiO2 whose dielectric constant is about 20 and is sandwitched by Cu films in an interposer. The on-interposer STO capacitors are directly connected to the LSI PADs so that they provide large decoupling capacitance without package leadframe/bonding wire inductance, resulting in the reduction of the resonant power supply noise. The measured power supply waveforms show significant reduction of the power supply noise, and the Shmoo plots also show the contribution of the STO capacitors to the robust operations of LSIs.

A forward/reverse body bias generator (BBG) which operates under wide supply-range is proposed. Fine-grained body biasing (FGBB) is effective to reduce variability and increase energy efficiency on digital LSIs. Since FGBB requires a number of BBGs to be implemented, simple design is preferred. We propose a BBG with charge pumps for reverse body bias and the BBG operates under wide supply-range from 0.5,V to 1.2,V. Layout of the BBG was designed in a cell-based flow with an AES core and fabricated in a 65~nm CMOS process. Area of the AES core is 0.22 mm$^2$ and area overhead of the BBG is 2.3%. Demonstration of the AES core shows a successful operation with the supply voltage from 0.5,V to 1.2,V which enables the reduction of power dissipation, for example, of 17% at 400,MHz operation.

Cell voltage equalizers are necessary to ensure years of operation and maximize the chargeable/dischargeable energy of series-connected supercapacitors (SCs). A two-switch voltage equalizer using a series-resonant voltage multiplier operating in frequency-multiplied discontinuous conduction mode (DCM) is proposed for series-connected SCs in this paper. The frequency-multiplied mode virtually increases the operation frequency and hence mitigates the negative impact of the impedance mismatch of capacitors on equalization performance, allowing multi-layer ceramic capacitors (MLCCs) to be used instead of bulky and costly tantalum capacitors, the conventional approach when using voltage multipliers in equalizers. Furthermore, the DCM operation inherently provides the constant current characteristic, realizing the excessive current protection that is desirable for SCs, which experience 0V and equivalently become an equivalent short-circuit load. Experimental equalization tests were performed for eight SCs connected in series under two frequency conditions to verify the improved equalization performance at the increased virtual operation frequencies. The standard deviation of cell voltages under the higher-frequency condition was lower than that under the lower-frequency condition, demonstrating superior equalization performance at higher frequencies.