Low-Voltage Operation of a High-Resistivity Load SOI SRAM Cell by Reduced Back-Gate-Bias Effect

Yasuo YAMAGUCHI; Jun TAKAHASHI; Takehisa YAMAGUCHI; Tomohisa WADA; Toshiaki IWAMATSU; Hans-Oliver JOACHIM; Yasuo INOUE; Tadashi NISHIMURA; Natsuro TSUBOUCHI

Low-Voltage Operation of a High-Resistivity Load SOI SRAM Cell by Reduced Back-Gate-Bias Effect

Yasuo YAMAGUCHI, Jun TAKAHASHI, Takehisa YAMAGUCHI, Tomohisa WADA, Toshiaki IWAMATSU, Hans-Oliver JOACHIM, Yasuo INOUE, Tadashi NISHIMURA, Natsuro TSUBOUCHI

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The stability of a high-resistivity load SRAM cell using thin-film SOI MOSFET's was investigated as compared with bulk-Si MOSFET's. In SOI MOSFET's back-gate-bias effect was suppressed by indirect application of back-gate-bias to the channel region through the thick buried oxide. The V_t shifts were reduced to be 10% and 14% of that in bulk-Si MOSFET's in partially and fully depleted devices, respectively. The reduction of back-gate-bias effect provides improvement of "high" output voltage and gain in the enhancement-enhancement (EE) inverter in a high-resistivity load SRAM cell, thereby offering improved cell stability. It was demonstrated by using partially depleted SOI SRAM cells that non-destructive reading was obtained even at a low drain voltage of 1.4 V without gate-potential boost, which was much smaller than the operation limit in a bulk Si SRAM with the same patterns and dimensions used as a reference. This implies that SOI devices can also offer low-voltage operation even in TFT-load cells used in up-to-date high-density SRAM's. These results suggest that thin-film SOI MOSFET's have a superior potential of low-voltage operation expected for further scaled devices and/or for portable systems in a forthcoming multimedia era.

Publication: IEICE TRANSACTIONS on Electronics Vol.E78-C No.7 pp.812-817

Publication Date: 1995/07/25

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Type of Manuscript: Special Section PAPER (Special Issue on LSI Memory Device, Circuit, Architecture and Application Technologies for Multimedia Age)

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Yasuo YAMAGUCHI, Jun TAKAHASHI, Takehisa YAMAGUCHI, Tomohisa WADA, Toshiaki IWAMATSU, Hans-Oliver JOACHIM, Yasuo INOUE, Tadashi NISHIMURA, Natsuro TSUBOUCHI, "Low-Voltage Operation of a High-Resistivity Load SOI SRAM Cell by Reduced Back-Gate-Bias Effect" in IEICE TRANSACTIONS on Electronics, vol. E78-C, no. 7, pp. 812-817, July 1995, doi: .
Abstract: The stability of a high-resistivity load SRAM cell using thin-film SOI MOSFET's was investigated as compared with bulk-Si MOSFET's. In SOI MOSFET's back-gate-bias effect was suppressed by indirect application of back-gate-bias to the channel region through the thick buried oxide. The V_t shifts were reduced to be 10% and 14% of that in bulk-Si MOSFET's in partially and fully depleted devices, respectively. The reduction of back-gate-bias effect provides improvement of "high" output voltage and gain in the enhancement-enhancement (EE) inverter in a high-resistivity load SRAM cell, thereby offering improved cell stability. It was demonstrated by using partially depleted SOI SRAM cells that non-destructive reading was obtained even at a low drain voltage of 1.4 V without gate-potential boost, which was much smaller than the operation limit in a bulk Si SRAM with the same patterns and dimensions used as a reference. This implies that SOI devices can also offer low-voltage operation even in TFT-load cells used in up-to-date high-density SRAM's. These results suggest that thin-film SOI MOSFET's have a superior potential of low-voltage operation expected for further scaled devices and/or for portable systems in a forthcoming multimedia era.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/e78-c_7_812/_p

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@ARTICLE{e78-c_7_812,
author={Yasuo YAMAGUCHI, Jun TAKAHASHI, Takehisa YAMAGUCHI, Tomohisa WADA, Toshiaki IWAMATSU, Hans-Oliver JOACHIM, Yasuo INOUE, Tadashi NISHIMURA, Natsuro TSUBOUCHI, },
journal={IEICE TRANSACTIONS on Electronics},
title={Low-Voltage Operation of a High-Resistivity Load SOI SRAM Cell by Reduced Back-Gate-Bias Effect},
year={1995},
volume={E78-C},
number={7},
pages={812-817},
abstract={The stability of a high-resistivity load SRAM cell using thin-film SOI MOSFET's was investigated as compared with bulk-Si MOSFET's. In SOI MOSFET's back-gate-bias effect was suppressed by indirect application of back-gate-bias to the channel region through the thick buried oxide. The V_t shifts were reduced to be 10% and 14% of that in bulk-Si MOSFET's in partially and fully depleted devices, respectively. The reduction of back-gate-bias effect provides improvement of "high" output voltage and gain in the enhancement-enhancement (EE) inverter in a high-resistivity load SRAM cell, thereby offering improved cell stability. It was demonstrated by using partially depleted SOI SRAM cells that non-destructive reading was obtained even at a low drain voltage of 1.4 V without gate-potential boost, which was much smaller than the operation limit in a bulk Si SRAM with the same patterns and dimensions used as a reference. This implies that SOI devices can also offer low-voltage operation even in TFT-load cells used in up-to-date high-density SRAM's. These results suggest that thin-film SOI MOSFET's have a superior potential of low-voltage operation expected for further scaled devices and/or for portable systems in a forthcoming multimedia era.},
keywords={},
doi={},
ISSN={},
month={July},}

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TY - JOUR
TI - Low-Voltage Operation of a High-Resistivity Load SOI SRAM Cell by Reduced Back-Gate-Bias Effect
T2 - IEICE TRANSACTIONS on Electronics
SP - 812
EP - 817
AU - Yasuo YAMAGUCHI
AU - Jun TAKAHASHI
AU - Takehisa YAMAGUCHI
AU - Tomohisa WADA
AU - Toshiaki IWAMATSU
AU - Hans-Oliver JOACHIM
AU - Yasuo INOUE
AU - Tadashi NISHIMURA
AU - Natsuro TSUBOUCHI
PY - 1995
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E78-C
IS - 7
JA - IEICE TRANSACTIONS on Electronics
Y1 - July 1995
AB - The stability of a high-resistivity load SRAM cell using thin-film SOI MOSFET's was investigated as compared with bulk-Si MOSFET's. In SOI MOSFET's back-gate-bias effect was suppressed by indirect application of back-gate-bias to the channel region through the thick buried oxide. The V_t shifts were reduced to be 10% and 14% of that in bulk-Si MOSFET's in partially and fully depleted devices, respectively. The reduction of back-gate-bias effect provides improvement of "high" output voltage and gain in the enhancement-enhancement (EE) inverter in a high-resistivity load SRAM cell, thereby offering improved cell stability. It was demonstrated by using partially depleted SOI SRAM cells that non-destructive reading was obtained even at a low drain voltage of 1.4 V without gate-potential boost, which was much smaller than the operation limit in a bulk Si SRAM with the same patterns and dimensions used as a reference. This implies that SOI devices can also offer low-voltage operation even in TFT-load cells used in up-to-date high-density SRAM's. These results suggest that thin-film SOI MOSFET's have a superior potential of low-voltage operation expected for further scaled devices and/or for portable systems in a forthcoming multimedia era.
ER -