A new, simple test circuit for measuring the threshold voltage distribution of flash EEPROM cell transistors is described. This circuit makes it possible to perform a reliability test for a large number of memory cell transistors with easy static operation because it reduces the measuring time drastically. In addition, this circuit can measure the highest and lowest thresh-old voltages of memory cell transistors easily. This method is suitable for performing the reliability test, such as program/erase endurance test and data retention test, for a large number of flash memory cell transistors. The usefulness of this new test circuit has been confirmed by applying it to 64 Kbit NAND-type flash memory cell array.

Effects of field edge steps on characteristics of MOSFETs with tungsten polycide stacked gate electrodes patterned by KrF excimer laser lithography was studied through an electrical gate length measurement technique. Sheet resistance of the gate electrodes on the field oxide, on the active region and across the field edge steps was determined from the relationship between gate conductance and designed gate linewidth. The sheet resistance of the gate electrode across the field edge steps was larger than that on the flat regions. Effects of field edge steps on gate linewidth variation were evaluated by SEM observations and electrical measurements. Distribution of gate linewidth in a wafer was measured by the MOSFET test structures with the linewidth down to sub-quarter micron. Gate linewidth variation near the field edge steps was found to influence the short channel MOSFET characteristics.

ElectroStatic Discharge (ESD) testing of integrated circuits subjects circuit elements to very high currents for short periods of time. A modified Transmission Line Pulse (TLP) measurement system for characterizing transistors and other circuit elements under high currents for ESD performance prediction and understanding is presented which can both stress devices and measure leakage. For the TLP system to yield useful information test structures are needed which vary the important design parameters for the circuit elements. Guidelines for transistor test structure design for use with the system are presented and demonstrated for PMOS transistors.

A simplified distribution base resistance model (SDM) is proposed to identify each component of the base resistance and determine the dominant. This model divides the parasitic base resistance into one straight path and two surrounding paths. It is clarified that the link base resistance is dominant in a short emitter and the surrounding polysilicon base electrode resistance is dominant in a long emitter. In the SDM, the distance of the link base is reduced to half; with metal silicide as the extrinsic base electrode, the base resistance will be reduced to 75%.

The electrical characteristics of sealed CMOSFETs with gates crossing sources/drains at 90 and 45 are experimentally investigated using test devices fabricated by an n-well CMOS process with trench isolation. Gain factors of surface-channel 90 and 45 n-MOSFETs can be estimated by a simple correction theory based on the combination of a center MOSFET and two edge MOSFETs. However, relatively large departures from the theory are observed in buried-channel 90 and 45 p-MOSFETs with widths less than the channel length. The difference between n- and p-MOSFETs is mainly due to the channel type. Other basic device parameters such as saturation drain currents, threshold voltages, subthreshold swings, maximum substrate currents and substrate-voltage dependence of threshold voltages are also measured and qualitatively explained.

Soft-error immunity of a 1-V operating CMOS memory cell is described. To evaluate the immunity precisely at the supply voltage of 1 V, a multi-threshold CMOS (MTCMOS) memory scheme, which has a peripheral circuit combining low-threshold CMOS logic gates and high-threshold MOSFETs with a virtual supply line, is adopted as a test structure. A 1-kb memory was designed and fabricated with 0.5-µm MTCMOS technology and the soft-error immunity of the memory cells was evaluated. The results of an alpha-particle exposure test and a pulse laser test show that a full-CMOS memory cell has high immunity at 1-V operations.

Threshold voltage shift in high frequency operation of 0.3µm and 0.35µm gate SOI CMOS is experimentally studied, using supply current measurement of inverter chains as test structures. The threshold voltage shift is obtained from the measurement of the leak currents in DC and high frequency condition. For a large supply voltage the electron-hole generation current becomes dominant, resulting in lowered threshold voltage, while the threshold voltage becomes higher than DC case for a low supply voltage. A reasonable relation of the threshold voltage shift and average electric field in the channel is obtained in this study. This method will be useful as a measure of "substrate current" for floating body SOI CMOS.

The quality of Si substrates affecting the oxide reliability was investigated using various kinds of test structures like flat capacitor, field edge array and gate edge array. The field edge array test structure which resembles the conditions found for real device is shown to be quite effective to determine the quality of oxides. Oxide grown on a P type epitaxial layer on P⁺ silicon substrate shows the highest reliability in all test structures. Gettering of heavy metals and/or crystal defects by the P⁺ silicon substrate is the dominant mechanism for the improvement of the oxide reliability. H₂ annealed silicon shows a good reliability if monitored using the flat capacitor. However, using the field edge array test structure, which is strongly influenced by real device process, the reliability of the oxide grown on H₂ annealed silicon degrades.

A novel technique for evaluation of charge build-up in semiconductor wafer processing such as ion implantation, plasma etching and plasma enhanced chemical vapor deposition by using the breakdown of MOS capacitors with charge collecting electrodes (antenna) is proposed. The charge build-up during high beam current ion implantation is successfully evaluated by using this technique. The breakdown sensitivity of a MOS capacitor is improved by using a small area MOS capacitor with a large area antenna electrode. To estimate charge build-up on wafers quantitatively, the best combination of gate oxide thickness, substrate type, MOS capacitor area and antenna ratio should be carefully chosen for individual charge build-up situation. The optimum structured antenna MOS capacitors which relationship between Q_BD and stressing current density was well characterized give us very simple and quantitative charge build-up evaluation. This technique is very simple and useful to estimate charge build-up as compared with conventional technique by suing EEPROM devices or large area MOS capacitors.

A test structure has been developed with very low-level current measurement technique and is used to evaluate a very small change of leakage current caused by the trapping and detrapping of electrons or holes. The present technique realizes detection of very low levels of leakage current (minimum detectable current is 510^-17 A), which is necessary in the course of evaluating gate oxides. This technique is very useful for the evaluation of retention characteristics and stress induced degradation of gate oxides.

The degradation of I-V characteristics under constant emitter-base reverse voltage stress in advanced self-aligned bipolar transistors was analyzed. Experimental analyses have been taken the stress field effect into account when predicting hot-carrier degradation. These analyses showed that base current starts to increase when the reverse voltage stress is about 3 V. The dependence of the base current change on reverse voltages of more than 3 V was also investigated experimentally, and equations expressing hot-carrier degradation in terms of the exponential dependence of excess base current on both reverse stress voltage and stress-enhancing voltage related to emitter-base breakdown voltage were derived.

The objective, when mapping a wafer, is to capture the the full variation across the wafer while minimising the number of measurements. This is a very similar objective to that of experimental design and this paper applies classical Design Of Experiment (DOE) techniques to the selection of measurement points for wafer mapping. The resulting measurements are then fitted using Response Surface Methodology (RSM) from which contour plots or wafer maps can be generated. The accuracy of the fit can be ascertained by inspection of the adjusted R² value and it is demonstrated that in many cases transformations can be used to improve the accuracy of the resulting wafer maps.

A new methodology for simulation-based CMOS process design has been proposed, using a Hierarchical Response Surface Method (HRSM) and an efficient experimental calibration. The design methodology has been verified using a 0.4 micron CMOS process. The proposed HRSM achieved a 60% reduction of process and device design cost in comparison with those of conventional TCAD. The procedure was performed in conjunction with an experimental calibration technique to provide a reliable threshold voltage prediction including process variation effects. The total CPU cost was 200 hr. on SUN SPARC 10 and the error of the predicted threshold voltage was less than 0.02 V.

An architecture for a high-density nonvolatile memory with ferroelectric capacitors is proposed and simulated. The architecture includes: (1) the operation procedure for DRAM-like memory cells with a V_cc/2 common plate, (2) commands and pin arrangement compatible with those of DRAMs. The resulting ferroelectric memory is expected to show, in addition to nonvolatility, high performance in terms of speed, active power dissipation, and read endurance. In addition, the memory can be handled in the same way as DRAMs. The proposed basic operations are confirmed by using circuit simulations, in which an equivalent circuit model for ferroelectirc capacitors is incorporated. A problem remaining with the architecture is low write endurance due to fatigue along with polarization switching. Designing the reference-voltage generator for 1T1C (one-transistor and one-capacitor) cells, while considering signal reduction along with fatigue, will be another issue for achieving high-density comparable to that of DRAMs.

One of coupling coefficients appearing in the coupled power equations describing the crosstalk in an image fiber is derived based on the coupled mode theory. Cores arranged in the cross-section of the fiber differ randomly to the degree of several percent in size and consequently modes propagating along the cores differ randomly. Random fluctuations of the propagation constants of modes cause the random transfer process of power between the cores, whereas contributions of the random fluctuations of the mode coupling coefficients to the statistical process can be neglected. The coupling coefficient is described as the ratio of the power transfer ratio to the coupling length for two cores with slightly different radii characterizing the random cores. The theoretical results are in good agreement with measurement results except near cutoff.

New series expressing the radiation fields from both axial and circumferential slots on a circular conducting cylinder are derived. These new series converge rapidly even for near fields. This letter includes useful figures showing characteristics of near fields calculated numerically using the new series.