Over 40-Gbit/s InP HEMT ICs for Optical Communication Systems

Toshihide SUZUKI; Yasuhiro NAKASHA; Hideki KANO; Masaru SATO; Satoshi MASUDA; Ken SAWADA; Kozo MAKIYAMA; Tsuyoshi TAKAHASHI; Tatsuya HIROSE; Naoki HARA; Masahiko TAKIGAWA

Over 40-Gbit/s InP HEMT ICs for Optical Communication Systems

Toshihide SUZUKI, Yasuhiro NAKASHA, Hideki KANO, Masaru SATO, Satoshi MASUDA, Ken SAWADA, Kozo MAKIYAMA, Tsuyoshi TAKAHASHI, Tatsuya HIROSE, Naoki HARA, Masahiko TAKIGAWA

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In this paper, we describe the operation of circuits capable of more than 40-Gbit/s that we have developed using InP HEMT technology. For example, we succeeded in obtaining 43-Gbit/s operation for a full-rate 4:1Multiplier (MUX), 50-Gbit/s operation for a Demultiplexer (DEMUX), 50-Gbit/s operation for a D-type flip-flop (D-FF), and a preamplifier with a bandwidth of 40 GHz. In addition, the achievement of 90-Gbit/s operation for a 2:1MUX and a distributed amplifier with over 110-GHz bandwidth indicates that InP HEMT technology is promising for system operations of over 100 Gbit/s. To achieve these results, we also developed several design techniques to improve frequency response above 80 GHz including a symmetric and separated layout of differential elements in the basic SCFL gate and inverted microstrip.

Publication: IEICE TRANSACTIONS on Electronics Vol.E86-C No.10 pp.1916-1922

Publication Date: 2003/10/01

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Type of Manuscript: Special Section INVITED PAPER (Special Issue on Heterostructure Microelectronics with TWHM2003)

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Toshihide SUZUKI, Yasuhiro NAKASHA, Hideki KANO, Masaru SATO, Satoshi MASUDA, Ken SAWADA, Kozo MAKIYAMA, Tsuyoshi TAKAHASHI, Tatsuya HIROSE, Naoki HARA, Masahiko TAKIGAWA, "Over 40-Gbit/s InP HEMT ICs for Optical Communication Systems" in IEICE TRANSACTIONS on Electronics, vol. E86-C, no. 10, pp. 1916-1922, October 2003, doi: .
Abstract: In this paper, we describe the operation of circuits capable of more than 40-Gbit/s that we have developed using InP HEMT technology. For example, we succeeded in obtaining 43-Gbit/s operation for a full-rate 4:1Multiplier (MUX), 50-Gbit/s operation for a Demultiplexer (DEMUX), 50-Gbit/s operation for a D-type flip-flop (D-FF), and a preamplifier with a bandwidth of 40 GHz. In addition, the achievement of 90-Gbit/s operation for a 2:1MUX and a distributed amplifier with over 110-GHz bandwidth indicates that InP HEMT technology is promising for system operations of over 100 Gbit/s. To achieve these results, we also developed several design techniques to improve frequency response above 80 GHz including a symmetric and separated layout of differential elements in the basic SCFL gate and inverted microstrip.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/e86-c_10_1916/_p

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@ARTICLE{e86-c_10_1916,
author={Toshihide SUZUKI, Yasuhiro NAKASHA, Hideki KANO, Masaru SATO, Satoshi MASUDA, Ken SAWADA, Kozo MAKIYAMA, Tsuyoshi TAKAHASHI, Tatsuya HIROSE, Naoki HARA, Masahiko TAKIGAWA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Over 40-Gbit/s InP HEMT ICs for Optical Communication Systems},
year={2003},
volume={E86-C},
number={10},
pages={1916-1922},
abstract={In this paper, we describe the operation of circuits capable of more than 40-Gbit/s that we have developed using InP HEMT technology. For example, we succeeded in obtaining 43-Gbit/s operation for a full-rate 4:1Multiplier (MUX), 50-Gbit/s operation for a Demultiplexer (DEMUX), 50-Gbit/s operation for a D-type flip-flop (D-FF), and a preamplifier with a bandwidth of 40 GHz. In addition, the achievement of 90-Gbit/s operation for a 2:1MUX and a distributed amplifier with over 110-GHz bandwidth indicates that InP HEMT technology is promising for system operations of over 100 Gbit/s. To achieve these results, we also developed several design techniques to improve frequency response above 80 GHz including a symmetric and separated layout of differential elements in the basic SCFL gate and inverted microstrip.},
keywords={},
doi={},
ISSN={},
month={October},}

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TY - JOUR
TI - Over 40-Gbit/s InP HEMT ICs for Optical Communication Systems
T2 - IEICE TRANSACTIONS on Electronics
SP - 1916
EP - 1922
AU - Toshihide SUZUKI
AU - Yasuhiro NAKASHA
AU - Hideki KANO
AU - Masaru SATO
AU - Satoshi MASUDA
AU - Ken SAWADA
AU - Kozo MAKIYAMA
AU - Tsuyoshi TAKAHASHI
AU - Tatsuya HIROSE
AU - Naoki HARA
AU - Masahiko TAKIGAWA
PY - 2003
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E86-C
IS - 10
JA - IEICE TRANSACTIONS on Electronics
Y1 - October 2003
AB - In this paper, we describe the operation of circuits capable of more than 40-Gbit/s that we have developed using InP HEMT technology. For example, we succeeded in obtaining 43-Gbit/s operation for a full-rate 4:1Multiplier (MUX), 50-Gbit/s operation for a Demultiplexer (DEMUX), 50-Gbit/s operation for a D-type flip-flop (D-FF), and a preamplifier with a bandwidth of 40 GHz. In addition, the achievement of 90-Gbit/s operation for a 2:1MUX and a distributed amplifier with over 110-GHz bandwidth indicates that InP HEMT technology is promising for system operations of over 100 Gbit/s. To achieve these results, we also developed several design techniques to improve frequency response above 80 GHz including a symmetric and separated layout of differential elements in the basic SCFL gate and inverted microstrip.
ER -