A 7-bit 1-GS/s Flash ADC with Background Calibration

Sanroku TSUKAMOTO; Masaya MIYAHARA; Akira MATSUZAWA

doi:10.1587/transele.E97.C.298

A 7-bit 1-GS/s Flash ADC with Background Calibration

Sanroku TSUKAMOTO, Masaya MIYAHARA, Akira MATSUZAWA

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A 7bit 1GS/s flash ADC using two bit active interpolation and background offset calibration is proposed and tested. It achieves background calibration using 36 pre-amplifiers with 139 comparators. To cancel the offset, two pre-amplifiers and 12 comparators are set to offline in turn while the others are operating. A two bit active interpolation design and an offset cancellation scheme are implemented in the latch stage. The interpolation and background calibration significantly reduce analog input signal as well as reference voltage load. Fabricated with the 90nm CMOS process, the proposed ADC consumes 95mW under a 1.2V power supply.

Publication: IEICE TRANSACTIONS on Electronics Vol.E97-C No.4 pp.298-307

Publication Date: 2014/04/01

Publicized

Online ISSN: 1745-1353

DOI: 10.1587/transele.E97.C.298

Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design,---,Architecture, Circuit, Device and Design Methodology)

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Authors

Sanroku TSUKAMOTO
  Tokyo Institute of Technology
Masaya MIYAHARA
  Tokyo Institute of Technology
Akira MATSUZAWA
  Tokyo Institute of Technology

Keyword

background calibration, ADC, offset cancel, interpolation

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Sanroku TSUKAMOTO, Masaya MIYAHARA, Akira MATSUZAWA, "A 7-bit 1-GS/s Flash ADC with Background Calibration" in IEICE TRANSACTIONS on Electronics, vol. E97-C, no. 4, pp. 298-307, April 2014, doi: 10.1587/transele.E97.C.298.
Abstract: A 7bit 1GS/s flash ADC using two bit active interpolation and background offset calibration is proposed and tested. It achieves background calibration using 36 pre-amplifiers with 139 comparators. To cancel the offset, two pre-amplifiers and 12 comparators are set to offline in turn while the others are operating. A two bit active interpolation design and an offset cancellation scheme are implemented in the latch stage. The interpolation and background calibration significantly reduce analog input signal as well as reference voltage load. Fabricated with the 90nm CMOS process, the proposed ADC consumes 95mW under a 1.2V power supply.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/transele.E97.C.298/_p

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@ARTICLE{e97-c_4_298,
author={Sanroku TSUKAMOTO, Masaya MIYAHARA, Akira MATSUZAWA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 7-bit 1-GS/s Flash ADC with Background Calibration},
year={2014},
volume={E97-C},
number={4},
pages={298-307},
abstract={A 7bit 1GS/s flash ADC using two bit active interpolation and background offset calibration is proposed and tested. It achieves background calibration using 36 pre-amplifiers with 139 comparators. To cancel the offset, two pre-amplifiers and 12 comparators are set to offline in turn while the others are operating. A two bit active interpolation design and an offset cancellation scheme are implemented in the latch stage. The interpolation and background calibration significantly reduce analog input signal as well as reference voltage load. Fabricated with the 90nm CMOS process, the proposed ADC consumes 95mW under a 1.2V power supply.},
keywords={},
doi={10.1587/transele.E97.C.298},
ISSN={1745-1353},
month={April},}

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TY - JOUR
TI - A 7-bit 1-GS/s Flash ADC with Background Calibration
T2 - IEICE TRANSACTIONS on Electronics
SP - 298
EP - 307
AU - Sanroku TSUKAMOTO
AU - Masaya MIYAHARA
AU - Akira MATSUZAWA
PY - 2014
DO - 10.1587/transele.E97.C.298
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E97-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2014
AB - A 7bit 1GS/s flash ADC using two bit active interpolation and background offset calibration is proposed and tested. It achieves background calibration using 36 pre-amplifiers with 139 comparators. To cancel the offset, two pre-amplifiers and 12 comparators are set to offline in turn while the others are operating. A two bit active interpolation design and an offset cancellation scheme are implemented in the latch stage. The interpolation and background calibration significantly reduce analog input signal as well as reference voltage load. Fabricated with the 90nm CMOS process, the proposed ADC consumes 95mW under a 1.2V power supply.
ER -