A Single Opamp Third-Order Low-Distortion Delta-Sigma Modulator with SAR Quantizer Embedded Passive Adder

I-Jen CHAO; Ching-Wen HOU; Bin-Da LIU; Soon-Jyh CHANG; Chun-Yueh HUANG

doi:10.1587/transele.E97.C.526

A Single Opamp Third-Order Low-Distortion Delta-Sigma Modulator with SAR Quantizer Embedded Passive Adder

I-Jen CHAO, Ching-Wen HOU, Bin-Da LIU, Soon-Jyh CHANG, Chun-Yueh HUANG

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A third-order low-distortion delta-sigma modulator (DSM), whose third-order noise-shaping ability is achieved by just a single opamp, is proposed. Since only one amplifier is required in the whole circuit, the designed DSM is very power efficient. To realize the adder in front of quantizer without employing the huge-power opamp, a capacitive passive adder, which is the digital-to-analog converter (DAC) array of a successive-approximation-type quantizer, is used. In addition, the feedback path timing is extended from a nonoverlapping interval for the conventional low-distortion structure to half of the clock period, so that the strict operation timing issue with regard to quantization and the dynamic element matching (DEM) logic operation can be solved. In the proposed DSM structure, the features of the unity-gain signal transfer function (STF) and finite-impulse-response (FIR) noise transfer function (NTF) are still preserved, and thus advantages such as a relaxed opamp slew rate and reduced output swing are also maintained, as with the conventional low-distortion DSM. Moreover, the memory effect in the proposed DSM is analyzed when employing the opamp sharing for integrators. The proposed third-order DSM with a 4-bit SAR ADC as the quantizer is implemented in a 90-nm CMOS process. The post-layout simulations show a 79.8-dB signal-to-noise and distortion ratio (SNDR) in the 1.875-MHz signal bandwidth (OSR=16). The active area of the circuit is 0.35mm² and total power consumption is 2.85mW, resulting in a figure of merit (FOM) of 95 fJ/conversion-step.

Publication: IEICE TRANSACTIONS on Electronics Vol.E97-C No.6 pp.526-537

Publication Date: 2014/06/01

Publicized

Online ISSN: 1745-1353

DOI: 10.1587/transele.E97.C.526

Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)

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Authors

I-Jen CHAO
  National Cheng Kung University
Ching-Wen HOU
  National Cheng Kung University
Bin-Da LIU
  National Cheng Kung University
Soon-Jyh CHANG
  National Cheng Kung University
Chun-Yueh HUANG
  National University of Tainan

Keyword

delta-sigma modulator, DSM, opamp sharing, relaxed dynamic element matching (DEM) timing

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I-Jen CHAO, Ching-Wen HOU, Bin-Da LIU, Soon-Jyh CHANG, Chun-Yueh HUANG, "A Single Opamp Third-Order Low-Distortion Delta-Sigma Modulator with SAR Quantizer Embedded Passive Adder" in IEICE TRANSACTIONS on Electronics, vol. E97-C, no. 6, pp. 526-537, June 2014, doi: 10.1587/transele.E97.C.526.
Abstract: A third-order low-distortion delta-sigma modulator (DSM), whose third-order noise-shaping ability is achieved by just a single opamp, is proposed. Since only one amplifier is required in the whole circuit, the designed DSM is very power efficient. To realize the adder in front of quantizer without employing the huge-power opamp, a capacitive passive adder, which is the digital-to-analog converter (DAC) array of a successive-approximation-type quantizer, is used. In addition, the feedback path timing is extended from a nonoverlapping interval for the conventional low-distortion structure to half of the clock period, so that the strict operation timing issue with regard to quantization and the dynamic element matching (DEM) logic operation can be solved. In the proposed DSM structure, the features of the unity-gain signal transfer function (STF) and finite-impulse-response (FIR) noise transfer function (NTF) are still preserved, and thus advantages such as a relaxed opamp slew rate and reduced output swing are also maintained, as with the conventional low-distortion DSM. Moreover, the memory effect in the proposed DSM is analyzed when employing the opamp sharing for integrators. The proposed third-order DSM with a 4-bit SAR ADC as the quantizer is implemented in a 90-nm CMOS process. The post-layout simulations show a 79.8-dB signal-to-noise and distortion ratio (SNDR) in the 1.875-MHz signal bandwidth (OSR=16). The active area of the circuit is 0.35mm² and total power consumption is 2.85mW, resulting in a figure of merit (FOM) of 95 fJ/conversion-step.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/transele.E97.C.526/_p

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@ARTICLE{e97-c_6_526,
author={I-Jen CHAO, Ching-Wen HOU, Bin-Da LIU, Soon-Jyh CHANG, Chun-Yueh HUANG, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Single Opamp Third-Order Low-Distortion Delta-Sigma Modulator with SAR Quantizer Embedded Passive Adder},
year={2014},
volume={E97-C},
number={6},
pages={526-537},
abstract={A third-order low-distortion delta-sigma modulator (DSM), whose third-order noise-shaping ability is achieved by just a single opamp, is proposed. Since only one amplifier is required in the whole circuit, the designed DSM is very power efficient. To realize the adder in front of quantizer without employing the huge-power opamp, a capacitive passive adder, which is the digital-to-analog converter (DAC) array of a successive-approximation-type quantizer, is used. In addition, the feedback path timing is extended from a nonoverlapping interval for the conventional low-distortion structure to half of the clock period, so that the strict operation timing issue with regard to quantization and the dynamic element matching (DEM) logic operation can be solved. In the proposed DSM structure, the features of the unity-gain signal transfer function (STF) and finite-impulse-response (FIR) noise transfer function (NTF) are still preserved, and thus advantages such as a relaxed opamp slew rate and reduced output swing are also maintained, as with the conventional low-distortion DSM. Moreover, the memory effect in the proposed DSM is analyzed when employing the opamp sharing for integrators. The proposed third-order DSM with a 4-bit SAR ADC as the quantizer is implemented in a 90-nm CMOS process. The post-layout simulations show a 79.8-dB signal-to-noise and distortion ratio (SNDR) in the 1.875-MHz signal bandwidth (OSR=16). The active area of the circuit is 0.35mm² and total power consumption is 2.85mW, resulting in a figure of merit (FOM) of 95 fJ/conversion-step.},
keywords={},
doi={10.1587/transele.E97.C.526},
ISSN={1745-1353},
month={June},}

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TY - JOUR
TI - A Single Opamp Third-Order Low-Distortion Delta-Sigma Modulator with SAR Quantizer Embedded Passive Adder
T2 - IEICE TRANSACTIONS on Electronics
SP - 526
EP - 537
AU - I-Jen CHAO
AU - Ching-Wen HOU
AU - Bin-Da LIU
AU - Soon-Jyh CHANG
AU - Chun-Yueh HUANG
PY - 2014
DO - 10.1587/transele.E97.C.526
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E97-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 2014
AB - A third-order low-distortion delta-sigma modulator (DSM), whose third-order noise-shaping ability is achieved by just a single opamp, is proposed. Since only one amplifier is required in the whole circuit, the designed DSM is very power efficient. To realize the adder in front of quantizer without employing the huge-power opamp, a capacitive passive adder, which is the digital-to-analog converter (DAC) array of a successive-approximation-type quantizer, is used. In addition, the feedback path timing is extended from a nonoverlapping interval for the conventional low-distortion structure to half of the clock period, so that the strict operation timing issue with regard to quantization and the dynamic element matching (DEM) logic operation can be solved. In the proposed DSM structure, the features of the unity-gain signal transfer function (STF) and finite-impulse-response (FIR) noise transfer function (NTF) are still preserved, and thus advantages such as a relaxed opamp slew rate and reduced output swing are also maintained, as with the conventional low-distortion DSM. Moreover, the memory effect in the proposed DSM is analyzed when employing the opamp sharing for integrators. The proposed third-order DSM with a 4-bit SAR ADC as the quantizer is implemented in a 90-nm CMOS process. The post-layout simulations show a 79.8-dB signal-to-noise and distortion ratio (SNDR) in the 1.875-MHz signal bandwidth (OSR=16). The active area of the circuit is 0.35mm² and total power consumption is 2.85mW, resulting in a figure of merit (FOM) of 95 fJ/conversion-step.
ER -