This paper presents a simple-structured tunable resonator employing semiconductor switches that can change its resonant frequency discretely but precisely. The tunable resonator comprises a transmission line with a comb-shaped pattern and multiple single-pole single-throw (SPST) switches placed between the teeth of the comb-shaped pattern. The resonator changes its resonant frequency according to the switch states, by controlling the path length carrying a high frequency current. The characteristics of the proposed resonator are evaluated through both method of moment electromagnetic simulation and fabrication, using GaAs FET SPST switches. The fabricated resonator changes its resonant frequency from 1.63 GHz to 1.85 GHz. This paper also introduces two circuit designs based on the proposed resonator that expands the tuning range of the resonant frequency or the number of resonant frequencies to be obtained.

A 60-GHz power amplifier (PA) with a reliability consideration for a hot-carrier-induced (HCI) degradation is presented. The supply voltage of the last stage of the PA (V_PA) is dynamically controlled by an on-chip digitally-assisted low drop-out voltage regulator (LDO) to alleviate HCI effects. A physical model for estimation of HCI degradation of NMOSFETs is discussed and investigated for dynamic operation. The PA is fabricated in a standard 65-nm CMOS process with a core area of 0.21 mm², which provides a saturation power of 10.1 dBm to 13.2 dBm with a peak power-added efficiency (PAE) of 8.1% to 15.0% for the supply voltage V_PA which varies from 0.7 V to 1.0 V at 60 GHz, respectively.

A novel auto-tuning digital DC--DC converter is presented. In order to reduce the recovery time and undershoot, the auto-tuning control combines LnL, conventional PID and a predictive PID with a configurable predictive coefficient. A switch module is used to select an algorithm from the three control algorithms, according to the difference between the error signal and the two initially predefined thresholds. The detection and control logic is designed for both window delay line ADC and Σ Δ DPWM to correct the delay deviation. When the output of the converter exceeds the quantization range, the digital output of ADC is set at 0 or 1, and the delay line stops working to reduce power consumption. Theoretical analysis and simulations in the CSMC CMOS 0.5 μm process are carried out to verify the proposed DC--DC converter. It is found that the converter achieves a power efficiency of more than 90% at heavy load, and reduces the recovery time and undershoot.

This paper proposes a new address method to reduce the address power consumption in an AC plasma panel display (AC-PDP). We apply an overlap scan method, in which the scan pulse overlaps with those of the previous scan time and the next scan time. The overlap scan method decreases the address voltage and consequently reduces the address power consumption. However, the drawback of this method is the narrow address voltage margin. This occurs because the maximum address voltage decreases much more than the minimum address voltage does. In order to increase the address voltage margin, we apply a two-step address voltage waveform, in the overlap scan method. In this case, the maximum address voltage increases; however, the minimum address voltage is almost the same. This leads to a wide address voltage margin. Moreover, the two-step address voltage waveform reduces the address power consumption, because the address voltage rises and falls in two steps using an energy recovery capacitor. Consequently, the experimental results show that the new address method reduces the address power consumption by 19.6 Wh (58%) when compared with the conventional method.

Ultra-wide band (UWB) radar has a great advantage for range resolution, and is suitable for 3-dimensional (3-D) imaging sensor, such as for rescue robots or surveillance systems, where an accurate 3-dimensional measurement, impervious to optical environments, is indispensable. However, in indoor sensing situations, an available aperture size is severely limited by obstacles such as collapsed furniture or rubles. Thus, an estimated region of target image often becomes too small to identify whether it is a human body or other object. To address this issue, we previously proposed the image expansion method based on the ellipse extrapolation, where the fitting space is converted from real space to data space defined by range points to enhance the extrapolation accuracy. Although this method achieves an accurate image expansion for some cases, by exploiting the feature of the efficient imaging method as range points migration (RPM), there are still many cases, where it cannot maintain sufficient extrapolation accuracy because it only employs the single scattered component for imaging. For more accurate extrapolation, this paper extends the above image expansion method by exploiting double-scattered signals between the target and the wall in an indoor environment. The results from numerical simulation validate that the proposed method significantly expands the extrapolated region for multiple elliptical objects, compared with that obtained using only single scattered signal.

In this paper, a 1.8-V 10-bit 100 MS/s successive approximation register (SAR) analog-to-digital converter (ADC) simulated in a TSMC 0.18-μm CMOS process is presented. By applying ten comparators followed by an asynchronous trigger logic, the proposed SAR ADC achieves high speed operation. Compared to the conventional SAR ADC, there is no significant delay in the digital feedback logic in this design. With the sampling rate limited only by the ten delays of the capacitor DAC settling and comparators quantization, the proposed SAR ADC achieves a peak SNDR of 61.2 dB at 100 MS/s and 80 MS/s, consuming 3.2 mW and 3.1 mW respectively.

A scalable low voltage signaling (SLVS) transmitter, with asymmetric impedance calibration, is proposed for mobile applications which require low power consumption. The voltage swing of the proposed SLVS transmitter is scalable from 40 mV to 440 mV. The proposed asymmetric impedance calibration asymmetrically controls the pull-up and pull-down drivers for the SLVS transmitter with an impedance of 50 Ω. This makes it possible to remove the additional regulator used to calibrate the impedance of an output driver by controlling the swing level of a pre-driver. It also maintains the common mode voltage at the center voltage level of the transmitted signal. The proposed SVLS transmitter is implemented using a 0.18-μm 1-poly 6-metal CMOS process with a 1.2-V supply. The active area and power consumption of the transmitter are 250 × 123 μ m² and 2.9 mW/Gb/s, respectively.